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[/] [mod_sim_exp/] [trunk/] [syn/] [xilinx/] [src/] [operands_sp.xco] - Diff between revs 71 and 94

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Rev 71 Rev 94
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##############################################################
##############################################################
#
#
# Xilinx Core Generator version 11.4
# Xilinx Core Generator version 14.4
# Date: Fri Mar 16 09:50:19 2012
# Date: Tue Jul  2 16:44:14 2013
#
#
##############################################################
##############################################################
#
#
#  This file contains the customisation parameters for a
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#  unexpected and unsupported behavior.
#
#
##############################################################
##############################################################
#
#
 
#  Generated from component: xilinx.com:ip:blk_mem_gen:7.3
 
#
 
##############################################################
 
#
# BEGIN Project Options
# BEGIN Project Options
SET addpads = False
SET addpads = false
SET asysymbol = True
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET createndf = false
SET designentry = VHDL
SET designentry = VHDL
SET device = xc6vlx240t
SET device = xc7z020
SET devicefamily = virtex6
SET devicefamily = zynq
SET flowvendor = Foundation_ISE
SET flowvendor = Foundation_ISE
SET formalverification = False
SET formalverification = false
SET foundationsym = False
SET foundationsym = false
SET implementationfiletype = Ngc
SET implementationfiletype = Ngc
SET package = ff1156
SET package = clg484
SET removerpms = False
SET removerpms = false
SET simulationfiles = Behavioral
SET simulationfiles = Behavioral
SET speedgrade = -1
SET speedgrade = -1
SET verilogsim = True
SET verilogsim = false
SET vhdlsim = True
SET vhdlsim = true
# END Project Options
# END Project Options
# BEGIN Select
# BEGIN Select
SELECT Block_Memory_Generator family Xilinx,_Inc. 3.3
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
# END Select
# END Select
# BEGIN Parameters
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET assume_synchronous_clk=false
 
CSET axi_id_width=4
 
CSET axi_slave_type=Memory_Slave
 
CSET axi_type=AXI4_Full
CSET byte_size=9
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET collision_warnings=ALL
CSET component_name=operands_sp
CSET component_name=operands_sp
CSET disable_collision_warnings=false
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecc=false
 
CSET ecctype=No_ECC
 
CSET enable_32bit_address=false
CSET enable_a=Always_Enabled
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET enable_b=Always_Enabled
CSET error_injection_type=Single_Bit_Error_Injection
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET fill_remaining_memory_locations=false
 
CSET interface_type=Native
CSET load_init_file=false
CSET load_init_file=false
 
CSET mem_file=no_Mem_file_loaded
CSET memory_type=Single_Port_RAM
CSET memory_type=Single_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET output_reset_value_b=0
Line 63... Line 74...
CSET port_b_enable_rate=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=50
CSET port_b_write_rate=50
CSET primitive=8kx2
CSET primitive=8kx2
CSET read_width_a=512
CSET read_width_a=512
CSET read_width_b=32
CSET read_width_b=32
 
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_memory_primitives=false
 
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET reset_type=SYNC
 
CSET softecc=false
 
CSET use_axi_id=false
 
CSET use_bram_block=Stand_Alone
CSET use_byte_write_enable=false
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=32
CSET write_depth_a=32
CSET write_width_a=32
CSET write_width_a=32
CSET write_width_b=32
CSET write_width_b=32
# END Parameters
# END Parameters
 
# BEGIN Extra information
 
MISC pkg_timestamp=2012-11-19T16:22:25Z
 
# END Extra information
GENERATE
GENERATE
# CRC: 13eb5650
# CRC: 1a5b155a
# CRC: 1a5b155a
# CRC: 1a5b155a

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