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[/] [mpmc8/] [trunk/] [rtl/] [mpmc10/] [mpmc10_resv_bit.sv] - Diff between revs 5 and 11
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| Rev 5 |
Rev 11 |
| Line 37... |
Line 37... |
import mpmc10_pkg::*;
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import mpmc10_pkg::*;
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// Reservation status bit
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// Reservation status bit
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module mpmc10_resv_bit(clk, state, wch, we, cr, adr, resv_ch, resv_adr, rb);
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module mpmc10_resv_bit(clk, state, wch, we, cr, adr, resv_ch, resv_adr, rb);
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input clk;
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input clk;
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input [3:0] state;
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input mpmc10_state_t state;
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input we;
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input we;
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input cr;
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input cr;
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input [3:0] wch;
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input [3:0] wch;
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input [31:0] adr;
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input [31:0] adr;
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input [3:0] resv_ch [0:mpmc10_pkg::NAR-1];
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input [3:0] resv_ch [0:mpmc10_pkg::NAR-1];
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input [31:0] resv_adr [0:mpmc10_pkg::NAR-1];
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input [31:0] resv_adr [0:mpmc10_pkg::NAR-1];
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output reg rb;
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output reg rb;
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integer n5;
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integer n5;
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always_ff @(posedge clk)
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always_ff @(posedge clk)
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if (state==mpmc10_pkg::IDLE) begin
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if (state==IDLE) begin
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if (we) begin
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if (we) begin
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if (cr) begin
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if (cr) begin
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rb <= mpmc10_pkg::FALSE;
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rb <= 1'b0;
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for (n5 = 0; n5 < mpmc10_pkg::NAR; n5 = n5 + 1)
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for (n5 = 0; n5 < mpmc10_pkg::NAR; n5 = n5 + 1)
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if ((resv_ch[n5]==wch) && (resv_adr[n5][31:5]==adr[31:5]))
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if ((resv_ch[n5]==wch) && (resv_adr[n5][31:5]==adr[31:5]))
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rb <= mpmc10_pkg::TRUE;
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rb <= 1'b1;
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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