| Line 161... |
Line 161... |
wire ch0_hit_s, ch1_hit_s, ch2_hit_s, ch3_hit_s;
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wire ch0_hit_s, ch1_hit_s, ch2_hit_s, ch3_hit_s;
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wire ch4_hit_s, ch5_hit_s, ch6_hit_s, ch7_hit_s;
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wire ch4_hit_s, ch5_hit_s, ch6_hit_s, ch7_hit_s;
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wire ch0_hit_ne, ch5_hit_ne;
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wire ch0_hit_ne, ch5_hit_ne;
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always_ff @(posedge mem_ui_clk)
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always_ff @(posedge mem_ui_clk)
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if (app_rd_data_valid)
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rd_data_r <= app_rd_data;
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rd_data_r <= app_rd_data;
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always_ff @(posedge mem_ui_clk)
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always_ff @(posedge mem_ui_clk)
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rd_data_valid_r <= app_rd_data_valid;
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rd_data_valid_r <= app_rd_data_valid;
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reg [19:0] rst_ctr;
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reg [19:0] rst_ctr;
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| Line 396... |
Line 397... |
always_comb
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always_comb
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begin
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begin
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ld.bte <= wishbone_pkg::LINEAR;
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ld.bte <= wishbone_pkg::LINEAR;
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ld.cti <= wishbone_pkg::CLASSIC;
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ld.cti <= wishbone_pkg::CLASSIC;
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ld.blen <= 'd0;
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ld.blen <= 'd0;
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ld.cyc <= fifoo.stb && !fifoo.we && rd_data_valid_r && (uch!=4'd0 && uch!=4'd5 && uch!=4'd15);
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ld.cyc <= fifoo.cyc && !fifoo.we && rd_data_valid_r && (uch!=4'd0 && uch!=4'd5 && uch!=4'd15);
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ld.stb <= fifoo.stb && !fifoo.we && rd_data_valid_r && (uch!=4'd0 && uch!=4'd5 && uch!=4'd15);
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ld.stb <= fifoo.stb && !fifoo.we && rd_data_valid_r && (uch!=4'd0 && uch!=4'd5 && uch!=4'd15);
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ld.we <= 1'b0;
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ld.we <= 1'b0;
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ld.adr <= {app_waddr[31:4],4'h0};
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ld.adr <= {app_waddr[31:4],4'h0};
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ld.dat <= {app_waddr[31:14],8'h00,rd_data_r}; // modified=false,tag = high order address bits
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ld.dat <= rd_data_r;
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ld.sel <= {36{1'b1}}; // update all bytes
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ld.sel <= {16{1'b1}}; // update all bytes
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end
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end
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reg ch0wack;
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reg ch0wack;
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reg ch1wack;
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reg ch1wack;
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reg ch2wack;
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reg ch2wack;
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| Line 695... |
Line 696... |
.strip_cnt(resp_strip_cnt),
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.strip_cnt(resp_strip_cnt),
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.addr_base(adr),
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.addr_base(adr),
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.addr(app_waddr)
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.addr(app_waddr)
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);
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);
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mpmc10_set_write_mask_wb uswm1
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(
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.clk(mem_ui_clk),
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.state(state),
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.we(fifoo.we),
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.sel(req_fifoo.sel[15:0]),
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.adr(adr|{req_strip_cnt[0],4'h0}),
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.mask(wmask)
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);
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mpmc10_mask_select unsks1
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mpmc10_mask_select unsks1
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(
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(
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.rst(mem_ui_rst),
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.rst(mem_ui_rst),
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.clk(mem_ui_clk),
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.clk(mem_ui_clk),
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.state(state),
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.state(state),
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.wmask(wmask),
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.we(fifoo.we),
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.wmask(req_fifoo.sel[15:0]),
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.mask(app_wdf_mask),
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.mask(app_wdf_mask),
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.mask2(mem_wdf_mask2)
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.mask2(mem_wdf_mask2)
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);
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);
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mpmc10_data_select #(.WID(128)) uds1
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mpmc10_data_select #(.WID(128)) uds1
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