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[/] [myblaze/] [trunk/] [rtl/] [execute.py] - Diff between revs 5 and 6

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Line 6... Line 6... 
    Execute Unit
 
    Execute Unit
 
 
 
 
 
    :copyright: Copyright (c) 2010 Jian Luo
 
    :copyright: Copyright (c) 2010 Jian Luo
 
    :author-email: jian.luo.cn(at_)gmail.com
 
    :author-email: jian.luo.cn(at_)gmail.com
 
    :license: LGPL, see LICENSE for details
 
    :license: LGPL, see LICENSE for details
 
    :revision: $Id: execute.py 5 2010-11-21 10:59:30Z rockee $
 
    :revision: $Id: execute.py 6 2010-11-21 23:18:44Z rockee $
 
"""
 
"""
 
 
 
 
 
from myhdl import *
 
from myhdl import *
 
from defines import *
 
from defines import *
 
from functions import *
 
from functions import *
 
from debug import *
 
 
 
 
 
 
 
def ExecuteUnit(
 
def ExecuteUnit(
 
        # Inputs
 
        # Inputs
 
        clock,
 
        clock,
 
        reset,
 
        reset,
Line 64... Line 63... 
        ex_mem_read,
 
        ex_mem_read,
 
        ex_mem_write,
 
        ex_mem_write,
 
        ex_program_counter,
 
        ex_program_counter,
 
        ex_transfer_size,
 
        ex_transfer_size,
 
 
 
 
 
        # Generic Parameters
 
        # Ports only for debug
 
        #CFG_IMEM_SIZE=16,
 
        of_instruction=0,
 
        #CFG_DMEM_WIDTH=32,
 
        ex_dat_a=0,
 
 
 
        ex_dat_b=0,
 
        # XXX: if __debug__:
 
        ex_instruction=0,
 
        #of_instruction,
 
        ex_reg_a=0,
 
        #ex_dat_a,
 
        ex_reg_b=0,
 
        #ex_dat_b,
 
 
 
        #ex_instruction,
 
 
 
        #ex_reg_a,
 
 
 
        #ex_reg_b,
 
 
 
 
 
 
 
    ):
 
    ):
 
    """
 
    """
 
    """
 
    """
 
    ex_r_carry = Signal(False)
 
    ex_r_carry = Signal(False)
 
    ex_r_flush_ex= Signal(False)
 
    ex_r_flush_ex= Signal(False)
 
 
 
 
 
    ex_r_alu_result = Signal(intbv(0)[32:])
 
    ex_r_alu_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
 
    ex_r_reg_d = Signal(intbv(0)[5:])
 
    ex_r_reg_d = Signal(intbv(0)[CFG_GPRF_SIZE:])
 
    ex_r_reg_write = Signal(False)
 
    ex_r_reg_write = Signal(False)
 
 
 
 
 
    ex_comb_r_carry = Signal(False)
 
    ex_comb_r_carry = Signal(False)
 
    ex_comb_r_flush_ex = Signal(False)
 
    ex_comb_r_flush_ex = Signal(False)
 
 
 
 
 
    ex_comb_r_alu_result = Signal(intbv(0)[32:])
 
    ex_comb_r_alu_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
 
    ex_comb_r_reg_d = Signal(intbv(0)[5:])
 
    ex_comb_r_reg_d = Signal(intbv(0)[CFG_GPRF_SIZE:])
 
    ex_comb_r_reg_write = Signal(False)
 
    ex_comb_r_reg_write = Signal(False)
 
 
 
 
 
    ex_comb_branch = Signal(False)
 
    ex_comb_branch = Signal(False)
 
    ex_comb_dat_d = Signal(intbv(0)[32:])
 
    ex_comb_dat_d = Signal(intbv(0)[CFG_DMEM_WIDTH:])
 
    ex_comb_flush_id = Signal(False)
 
    ex_comb_flush_id = Signal(False)
 
    ex_comb_mem_read = Signal(False)
 
    ex_comb_mem_read = Signal(False)
 
    ex_comb_mem_write = Signal(False)
 
    ex_comb_mem_write = Signal(False)
 
    ex_comb_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
 
    ex_comb_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
 
    ex_comb_transfer_size = Signal(transfer_size_type.WORD)
 
    ex_comb_transfer_size = Signal(transfer_size_type.WORD)
 
 
 
 
 
    #if __debug__:
 
    if __debug__:
 
        #ex_comb_dat_a = Signal(intbv(0)[CFG_DMEM_WIDTH:])
 
        ex_comb_dat_a = Signal(intbv(0)[CFG_DMEM_WIDTH:])
 
        #ex_comb_dat_b = Signal(intbv(0)[CFG_DMEM_WIDTH:])
 
        ex_comb_dat_b = Signal(intbv(0)[CFG_DMEM_WIDTH:])
 
        #ex_comb_instruction = Signal(intbv(0)[CFG_DMEM_WIDTH:])
 
        ex_comb_instruction = Signal(intbv(0)[CFG_DMEM_WIDTH:])
 
        #ex_comb_reg_a = Signal(intbv(0)[5:])
 
        ex_comb_reg_a = Signal(intbv(0)[CFG_GPRF_SIZE:])
 
        #ex_comb_reg_b = Signal(intbv(0)[5:])
 
        ex_comb_reg_b = Signal(intbv(0)[CFG_GPRF_SIZE:])
 
 
 
 
 
    @always_comb
 
    @always_comb
 
    def regout():
 
    def regout():
 
        ex_alu_result.next = ex_r_alu_result
 
        ex_alu_result.next = ex_r_alu_result
 
        ex_reg_d.next = ex_r_reg_d
 
        ex_reg_d.next = ex_r_reg_d
 
        ex_reg_write.next = ex_r_reg_write
 
        ex_reg_write.next = ex_r_reg_write
 
 
 
 
 
    cpu_clock = 0
 
    cpu_clock = 0
 
    @always(clock.posedge)
 
    @always(clock.posedge)
 
    def seq():
 
    def seq():
 
 
 
        """
 
 
 
        ExecUnit sequential logic
 
 
 
        """
 
        if reset:
 
        if reset:
 
            ex_r_carry.next = False
 
            ex_r_carry.next = False
 
            ex_r_flush_ex.next = False
 
            ex_r_flush_ex.next = False
 
 
 
 
 
            ex_r_alu_result.next = intbv(0)[32:]
 
            ex_r_alu_result.next = intbv(0)[CFG_DMEM_WIDTH:]
 
            ex_r_reg_d.next = intbv(0)[5:]
 
            ex_r_reg_d.next = intbv(0)[CFG_GPRF_SIZE:]
 
            ex_r_reg_write.next = False
 
            ex_r_reg_write.next = False
 
 
 
 
 
            ex_branch.next = False
 
            ex_branch.next = False
 
            ex_dat_d.next = intbv(0)[32:]
 
            ex_dat_d.next = intbv(0)[CFG_DMEM_WIDTH:]
 
            ex_flush_id.next = False
 
            ex_flush_id.next = False
 
            ex_mem_read.next = False
 
            ex_mem_read.next = False
 
            ex_mem_write.next = False
 
            ex_mem_write.next = False
 
            ex_program_counter.next = intbv(0)[CFG_IMEM_SIZE:]
 
            ex_program_counter.next = intbv(0)[CFG_IMEM_SIZE:]
 
            ex_transfer_size.next = transfer_size_type.WORD
 
            ex_transfer_size.next = transfer_size_type.WORD
Line 149... Line 147... 
            ex_mem_read.next = ex_comb_mem_read
 
            ex_mem_read.next = ex_comb_mem_read
 
            ex_mem_write.next = ex_comb_mem_write
 
            ex_mem_write.next = ex_comb_mem_write
 
            ex_program_counter.next = ex_comb_program_counter
 
            ex_program_counter.next = ex_comb_program_counter
 
            ex_transfer_size.next = ex_comb_transfer_size
 
            ex_transfer_size.next = ex_comb_transfer_size
 
 
 
 
 
        #if __debug__:
 
        if __debug__:
 
          #if enable:
 
          if enable:
 
            #ex_dat_a.next = ex_comb_dat_a
 
            ex_dat_a.next = ex_comb_dat_a
 
            #ex_dat_b.next = ex_comb_dat_b
 
            ex_dat_b.next = ex_comb_dat_b
 
            #ex_instruction.next = ex_comb_instruction
 
            ex_instruction.next = ex_comb_instruction
 
            #ex_reg_a.next = ex_comb_reg_a
 
            ex_reg_a.next = ex_comb_reg_a
 
            #ex_reg_b.next = ex_comb_reg_b
 
            ex_reg_b.next = ex_comb_reg_b
 
 
 
 
 
    @always_comb
 
    @always_comb
 
    def comb():
 
    def comb():
 
 
 
        """
 
 
 
        ExecUnit combinatorial logic
 
 
 
        """
 
        # Signals mapping
 
        # Signals mapping
 
        r_carry = False
 
        r_carry = False
 
        r_flush_ex = False
 
        r_flush_ex = False
 
 
 
 
 
        r_alu_result = intbv(0)[CFG_DMEM_WIDTH:]
 
        r_alu_result = intbv(0)[CFG_DMEM_WIDTH:]
 
        r_reg_d = intbv(0)[5:]
 
        r_reg_d = intbv(0)[CFG_GPRF_SIZE:]
 
        r_reg_write = False
 
        r_reg_write = False
 
 
 
 
 
        branch = False
 
        branch = False
 
        dat_d = intbv(0)[CFG_DMEM_WIDTH:]
 
        dat_d = intbv(0)[CFG_DMEM_WIDTH:]
 
        flush_id = False
 
        flush_id = False
Line 323... Line 324... 
            result[:] = concat(False, sign_extend16(alu_src_a, alu_src_a[15]))
 
            result[:] = concat(False, sign_extend16(alu_src_a, alu_src_a[15]))
 
            #result[:] = concat(False, sign_extend(alu_src_a, alu_src_a[15],
 
            #result[:] = concat(False, sign_extend(alu_src_a, alu_src_a[15],
 
                                                  #16, CFG_DMEM_WIDTH))
 
                                                  #16, CFG_DMEM_WIDTH))
 
        else:
 
        else:
 
            result[:] = 0
 
            result[:] = 0
 
            #if __debug__:
 
            if __debug__:
 
                #assert False, 'FATAL Error: Unsupported ALU operation'
 
                assert False, 'FATAL Error: Unsupported ALU operation'
 
 
 
 
 
        # Set carry register
 
        # Set carry register
 
        if of_carry_keep:
 
        if of_carry_keep:
 
            r_carry = bool(ex_r_carry) # bool() needs for signal type mismatch
 
            r_carry = bool(ex_r_carry) # bool() needs for signal type mismatch
 
        else:
 
        else:
Line 354... Line 355... 
            else:
 
            else:
 
                branch = False
 
                branch = False
 
 
 
 
 
        # Handle CMPU
 
        # Handle CMPU
 
        cmp_cond = alu_src_a[CFG_DMEM_WIDTH-1] ^ alu_src_b[CFG_DMEM_WIDTH-1]
 
        cmp_cond = alu_src_a[CFG_DMEM_WIDTH-1] ^ alu_src_b[CFG_DMEM_WIDTH-1]
 
        if of_operation and cmp_cond:
 
        if of_operation and bool(cmp_cond):
 
            ## Set MSB
 
            ## Set MSB
 
            msb = alu_src_a[CFG_DMEM_WIDTH-1]
 
            msb = alu_src_a[CFG_DMEM_WIDTH-1]
 
            r_alu_result[:] = concat(msb, result[CFG_DMEM_WIDTH-1:])
 
            r_alu_result[:] = concat(msb, result[CFG_DMEM_WIDTH-1:])
 
        else:
 
        else:
 
            r_alu_result[:] = result[CFG_DMEM_WIDTH:]
 
            r_alu_result[:] = result[CFG_DMEM_WIDTH:]
Line 383... Line 384... 
        ex_comb_mem_read.next = mem_read
 
        ex_comb_mem_read.next = mem_read
 
        ex_comb_mem_write.next = mem_write
 
        ex_comb_mem_write.next = mem_write
 
        ex_comb_program_counter.next = program_counter
 
        ex_comb_program_counter.next = program_counter
 
        ex_comb_transfer_size.next = transfer_size
 
        ex_comb_transfer_size.next = transfer_size
 
 
 
 
 
        #if __debug__:
 
        if __debug__:
 
        #ex_comb_dat_a.next = dat_a
 
            ex_comb_dat_a.next = dat_a
 
        #ex_comb_dat_b.next = dat_b
 
            ex_comb_dat_b.next = dat_b
 
        #ex_comb_instruction.next = of_instruction
 
            ex_comb_instruction.next = of_instruction
 
        #ex_comb_reg_a.next = of_reg_a
 
            ex_comb_reg_a.next = of_reg_a
 
        #ex_comb_reg_b.next = of_reg_b
 
            ex_comb_reg_b.next = of_reg_b
 
 
 
 
 
    return instances()
 
    return instances()
 
 
 
 
 
if __name__ == '__main__':
 
if __name__ == '__main__':
 
    clock = Signal(False)
 
    clock = Signal(False)
 
    reset = Signal(False)
 
    reset = Signal(False)
 
    enable = Signal(False)
 
    enable = Signal(False)
 
 
 
 
 
    dmem_data_in = Signal(intbv(0)[32:])
 
    dmem_data_in = Signal(intbv(0)[CFG_DMEM_WIDTH:])
 
 
 
 
 
    mm_alu_result = Signal(intbv(0)[32:])
 
    mm_alu_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
 
    mm_mem_read =  Signal(False)
 
    mm_mem_read =  Signal(False)
 
    mm_reg_d = Signal(intbv(0)[5:])
 
    mm_reg_d = Signal(intbv(0)[CFG_GPRF_SIZE:])
 
    mm_reg_write = Signal(False)
 
    mm_reg_write = Signal(False)
 
    mm_transfer_size = Signal(transfer_size_type.WORD)
 
    mm_transfer_size = Signal(transfer_size_type.WORD)
 
 
 
 
 
    gprf_dat_a = Signal(intbv(0)[32:])
 
    gprf_dat_a = Signal(intbv(0)[CFG_DMEM_WIDTH:])
 
    gprf_dat_b = Signal(intbv(0)[32:])
 
    gprf_dat_b = Signal(intbv(0)[CFG_DMEM_WIDTH:])
 
    gprf_dat_d = Signal(intbv(0)[32:])
 
    gprf_dat_d = Signal(intbv(0)[CFG_DMEM_WIDTH:])
 
 
 
 
 
    ex_flush_id = Signal(False)
 
    ex_flush_id = Signal(False)
 
    of_alu_op = Signal(alu_operation.ALU_ADD)
 
    of_alu_op = Signal(alu_operation.ALU_ADD)
 
    of_alu_src_a = Signal(src_type_a.REGA)
 
    of_alu_src_a = Signal(src_type_a.REGA)
 
    of_alu_src_b = Signal(src_type_b.REGB)
 
    of_alu_src_b = Signal(src_type_b.REGB)
 
    of_branch_cond = Signal(branch_condition.NOP)
 
    of_branch_cond = Signal(branch_condition.NOP)
 
    of_carry = Signal(carry_type.C_ZERO)
 
    of_carry = Signal(carry_type.C_ZERO)
 
    of_carry_keep = Signal(False)
 
    of_carry_keep = Signal(False)
 
    of_delay = Signal(False)
 
    of_delay = Signal(False)
 
    of_hazard = Signal(False)
 
    of_hazard = Signal(False)
 
    of_immediate = Signal(intbv(0)[32:])
 
    of_immediate = Signal(intbv(0)[CFG_DMEM_WIDTH:])
 
    of_mem_read = Signal(False)
 
    of_mem_read = Signal(False)
 
    of_mem_write = Signal(False)
 
    of_mem_write = Signal(False)
 
    of_operation = Signal(False)
 
    of_operation = Signal(False)
 
    of_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
 
    of_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
 
    of_reg_a = Signal(intbv(0)[5:])
 
    of_reg_a = Signal(intbv(0)[CFG_GPRF_SIZE:])
 
    of_reg_b = Signal(intbv(0)[5:])
 
    of_reg_b = Signal(intbv(0)[CFG_GPRF_SIZE:])
 
    of_reg_d = Signal(intbv(0)[5:])
 
    of_reg_d = Signal(intbv(0)[CFG_GPRF_SIZE:])
 
    of_reg_write = Signal(False)
 
    of_reg_write = Signal(False)
 
    of_transfer_size = Signal(transfer_size_type.WORD)
 
    of_transfer_size = Signal(transfer_size_type.WORD)
 
 
 
    # Write back stage forwards
 
 
 
    of_fwd_mem_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
 
 
 
    of_fwd_reg_d = Signal(intbv(0)[CFG_GPRF_SIZE:])
 
 
 
    of_fwd_reg_write = Signal(False)
 
 
 
 
 
    ex_alu_result = Signal(intbv(0)[32:])
 
    ex_alu_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
 
    ex_reg_d = Signal(intbv(0)[5:])
 
    ex_reg_d = Signal(intbv(0)[CFG_GPRF_SIZE:])
 
    ex_reg_write = Signal(False)
 
    ex_reg_write = Signal(False)
 
 
 
 
 
    ex_branch = Signal(False)
 
    ex_branch = Signal(False)
 
    ex_dat_d = Signal(intbv(0)[32:])
 
    ex_dat_d = Signal(intbv(0)[CFG_DMEM_WIDTH:])
 
    ex_flush_id = Signal(False)
 
    ex_flush_id = Signal(False)
 
    ex_mem_read = Signal(False)
 
    ex_mem_read = Signal(False)
 
    ex_mem_write = Signal(False)
 
    ex_mem_write = Signal(False)
 
    ex_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
 
    ex_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
 
    ex_transfer_size = Signal(transfer_size_type.WORD)
 
    ex_transfer_size = Signal(transfer_size_type.WORD)
 
 
 
 
 
    kw = dict(
 
    kw = dict(
 
        func=ExecuteUnit,
 
 
 
        clock=clock,
 
        clock=clock,
 
        reset=reset,
 
        reset=reset,
 
        enable=enable,
 
        enable=enable,
 
        dmem_data_in=dmem_data_in,
 
        dmem_data_in=dmem_data_in,
 
        gprf_dat_a=gprf_dat_a,
 
        gprf_dat_a=gprf_dat_a,
Line 472... Line 476... 
        of_reg_a=of_reg_a,
 
        of_reg_a=of_reg_a,
 
        of_reg_b=of_reg_b,
 
        of_reg_b=of_reg_b,
 
        of_reg_d=of_reg_d,
 
        of_reg_d=of_reg_d,
 
        of_reg_write=of_reg_write,
 
        of_reg_write=of_reg_write,
 
        of_transfer_size=of_transfer_size,
 
        of_transfer_size=of_transfer_size,
 
 
 
        # Write back stage forwards
 
 
 
        of_fwd_mem_result=of_fwd_mem_result,
 
 
 
        of_fwd_reg_d=of_fwd_reg_d,
 
 
 
        of_fwd_reg_write=of_fwd_reg_write,
 
        # Outputs
 
        # Outputs
 
        ex_alu_result=ex_alu_result,
 
        ex_alu_result=ex_alu_result,
 
        ex_reg_d=ex_reg_d,
 
        ex_reg_d=ex_reg_d,
 
        ex_reg_write=ex_reg_write,
 
        ex_reg_write=ex_reg_write,
 
 
 
 
Line 485... Line 493... 
        ex_mem_read=ex_mem_read,
 
        ex_mem_read=ex_mem_read,
 
        ex_mem_write=ex_mem_write,
 
        ex_mem_write=ex_mem_write,
 
        ex_program_counter=ex_program_counter,
 
        ex_program_counter=ex_program_counter,
 
        ex_transfer_size=ex_transfer_size,
 
        ex_transfer_size=ex_transfer_size,
 
    )
 
    )
 
    toVerilog(**kw)
 
    toVerilog(ExecuteUnit, **kw)
 
    toVHDL(**kw)
 
    toVHDL(ExecuteUnit, **kw)
 
 
 
 
 
### EOF ###
 
### EOF ###
 
# vim:smarttab:sts=4:ts=4:sw=4:et:ai:tw=80:
 
# vim:smarttab:sts=4:ts=4:sw=4:et:ai:tw=80:
 
 
 
 
 
 
 
 
 
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