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https://opencores.org/ocsvn/nand_controller/nand_controller/trunk
[/] [nand_controller/] [trunk/] [VHDL/] [nand_master.vhd] - Diff between revs 18 and 19
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| Rev 18 |
Rev 19 |
| Line 274... |
Line 274... |
(state = MI_BYPASS_DATA_RD and substate = MS_BEGIN) else -- reading byte directly from the chip
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(state = MI_BYPASS_DATA_RD and substate = MS_BEGIN) else -- reading byte directly from the chip
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'0';
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'0';
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-- Activation of write byte mechanism
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-- Activation of write byte mechanism
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io_wr_activate <= '1' when (state = M_NAND_PAGE_PROGRAM and substate = MS_WRITE_DATA3) or -- initiate byte write for PAGE_PROGRAM command
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io_wr_activate <= '1' when (state = M_NAND_PAGE_PROGRAM and substate = MS_WRITE_DATA3) or -- initiate byte write for PAGE_PROGRAM command
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(state = MI_BYPASS_DATA_WR and substate = MS_WRITE_DATA0) else
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(state = MI_BYPASS_DATA_WR and substate = MS_WRITE_DATA0) else -- writing byte directly to the chip
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'0';
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'0';
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MASTER: process(clk, nreset, activate, cmd_in, data_in, state_switch)
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MASTER: process(clk, nreset, activate, cmd_in, data_in, state_switch)
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variable tmp_int : std_logic_vector(31 downto 0);
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variable tmp_int : std_logic_vector(31 downto 0);
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variable tmp : integer;
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variable tmp : integer;
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