| Line 311... |
Line 311... |
when M_NAND_RESET =>
|
when M_NAND_RESET =>
|
cle_data_in <= x"00ff";
|
cle_data_in <= x"00ff";
|
state <= M_WAIT;
|
state <= M_WAIT;
|
n_state <= M_IDLE;
|
n_state <= M_IDLE;
|
|
|
|
-- Read the status register of the controller
|
when MI_GET_STATUS =>
|
when MI_GET_STATUS =>
|
data_out <= status;
|
data_out <= status;
|
state <= M_IDLE;
|
state <= M_IDLE;
|
|
|
|
-- Set CE# to '0' (enable NAND chip)
|
when MI_CHIP_ENABLE =>
|
when MI_CHIP_ENABLE =>
|
nand_nce <= '0';
|
nand_nce <= '0';
|
state <= M_IDLE;
|
state <= M_IDLE;
|
status(2) <= '1';
|
status(2) <= '1';
|
|
|
|
-- Set CE# to '1' (disable NAND chip)
|
when MI_CHIP_DISABLE =>
|
when MI_CHIP_DISABLE =>
|
nand_nce <= '1';
|
nand_nce <= '1';
|
state <= M_IDLE;
|
state <= M_IDLE;
|
status(2) <= '0';
|
status(2) <= '0';
|
|
|
|
-- Set WP# to '0' (enable write protection)
|
when MI_WRITE_PROTECT =>
|
when MI_WRITE_PROTECT =>
|
nand_nwp <= '0';
|
nand_nwp <= '0';
|
status(3) <= '1';
|
status(3) <= '1';
|
state <= M_IDLE;
|
state <= M_IDLE;
|
|
|
|
-- Set WP# to '1' (disable write protection)
|
|
-- By default, this controller has WP# set to 0 on reset
|
when MI_WRITE_ENABLE =>
|
when MI_WRITE_ENABLE =>
|
nand_nwp <= '1';
|
nand_nwp <= '1';
|
status(3) <= '0';
|
status(3) <= '0';
|
state <= M_IDLE;
|
state <= M_IDLE;
|
|
|
|
-- Reset the index register.
|
|
-- Index register holds offsets into JEDEC ID, Parameter Page buffer or Data Page buffer depending on
|
|
-- the operation being performed
|
when MI_RESET_INDEX =>
|
when MI_RESET_INDEX =>
|
page_idx <= 0;
|
page_idx <= 0;
|
state <= M_IDLE;
|
state <= M_IDLE;
|
|
|
|
-- Read 1 byte from JEDEC ID and increment the index register.
|
|
-- If the value points outside the 5 byte JEDEC ID array,
|
|
-- the register is reset to 0 and bit 4 of the status register
|
|
-- is set to '1'
|
when MI_GET_ID_BYTE =>
|
when MI_GET_ID_BYTE =>
|
if(page_idx < 5)then
|
if(page_idx < 5)then
|
data_out <= chip_id(page_idx);
|
data_out <= chip_id(page_idx);
|
page_idx <= page_idx + 1;
|
page_idx <= page_idx + 1;
|
status(4) <= '0';
|
status(4) <= '0';
|
| Line 351... |
Line 364... |
page_idx <= 0;
|
page_idx <= 0;
|
status(4) <= '1';
|
status(4) <= '1';
|
end if;
|
end if;
|
state <= M_IDLE;
|
state <= M_IDLE;
|
|
|
|
-- Read 1 byte from 256 bytes buffer that holds the Parameter Page.
|
|
-- If the value goes beyond 255, then the register is reset and
|
|
-- bit 4 of the status register is set to '1'
|
when MI_GET_PARAM_PAGE_BYTE =>
|
when MI_GET_PARAM_PAGE_BYTE =>
|
if(page_idx < 256)then
|
if(page_idx < 256)then
|
data_out <= page_param(page_idx);
|
data_out <= page_param(page_idx);
|
page_idx <= page_idx + 1;
|
page_idx <= page_idx + 1;
|
status(4) <= '0';
|
status(4) <= '0';
|
| Line 363... |
Line 379... |
page_idx <= 0;
|
page_idx <= 0;
|
status(4) <= '1';
|
status(4) <= '1';
|
end if;
|
end if;
|
state <= M_IDLE;
|
state <= M_IDLE;
|
|
|
|
-- Read 1 byte from the buffer that holds the content of last read
|
|
-- page. The limit is variable and depends on the values in
|
|
-- the Parameter Page. In case the index register points beyond
|
|
-- valid page content, its value is reset and bit 4 of the status
|
|
-- register is set to '1'
|
when MI_GET_DATA_PAGE_BYTE =>
|
when MI_GET_DATA_PAGE_BYTE =>
|
if(page_idx < data_bytes_per_page + oob_bytes_per_page)then
|
if(page_idx < data_bytes_per_page + oob_bytes_per_page)then
|
data_out <= page_data(page_idx);
|
data_out <= page_data(page_idx);
|
page_idx <= page_idx + 1;
|
page_idx <= page_idx + 1;
|
status(4) <= '0';
|
status(4) <= '0';
|
| Line 375... |
Line 396... |
page_idx <= 0;
|
page_idx <= 0;
|
status(4) <= '1';
|
status(4) <= '1';
|
end if;
|
end if;
|
state <= M_IDLE;
|
state <= M_IDLE;
|
|
|
|
-- Write 1 byte into the Data Page buffer at offset specified by
|
|
-- the index register. If the value of the index register points
|
|
-- beyond valid page content, its value is reset and bit 4 of
|
|
-- the status register is set to '1'
|
when MI_SET_DATA_PAGE_BYTE =>
|
when MI_SET_DATA_PAGE_BYTE =>
|
if(page_idx < data_bytes_per_page + oob_bytes_per_page)then
|
if(page_idx < data_bytes_per_page + oob_bytes_per_page)then
|
page_data(page_idx) <= data_in;
|
page_data(page_idx) <= data_in;
|
page_idx <= page_idx + 1;
|
page_idx <= page_idx + 1;
|
status(4) <= '0';
|
status(4) <= '0';
|
| Line 386... |
Line 411... |
page_idx <= 0;
|
page_idx <= 0;
|
status(4) <= '1';
|
status(4) <= '1';
|
end if;
|
end if;
|
state <= M_IDLE;
|
state <= M_IDLE;
|
|
|
|
-- Gets the address byte specified by the index register. Bit 4
|
|
-- of the status register is set to '1' if the value of the index
|
|
-- register points beyond valid address data and the value of
|
|
-- the index register is reset
|
when MI_GET_CURRENT_ADDRESS_BYTE =>
|
when MI_GET_CURRENT_ADDRESS_BYTE =>
|
if(page_idx < addr_cycles)then
|
if(page_idx < addr_cycles)then
|
data_out <= current_address(page_idx);
|
data_out <= current_address(page_idx);
|
page_idx <= page_idx + 1;
|
page_idx <= page_idx + 1;
|
status(4) <= '0';
|
status(4) <= '0';
|
| Line 397... |
Line 426... |
page_idx <= 0;
|
page_idx <= 0;
|
status(4) <= '1';
|
status(4) <= '1';
|
end if;
|
end if;
|
state <= M_IDLE;
|
state <= M_IDLE;
|
|
|
|
-- Sets the value of the address byte specified by the index register.Bit 4
|
|
-- of the status register is set to '1' if the value of the index
|
|
-- register points beyond valid address data and the value of
|
|
-- the index register is reset
|
when MI_SET_CURRENT_ADDRESS_BYTE =>
|
when MI_SET_CURRENT_ADDRESS_BYTE =>
|
if(page_idx < addr_cycles)then
|
if(page_idx < addr_cycles)then
|
current_address(page_idx) <= data_in;
|
current_address(page_idx) <= data_in;
|
page_idx <= page_idx + 1;
|
page_idx <= page_idx + 1;
|
status(4) <= '0';
|
status(4) <= '0';
|
