# The NEO430 Processor
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# The NEO430 Processor
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[](https://travis-ci.com/stnolting/neo430)
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[](https://travis-ci.com/stnolting/neo430)
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[](https://github.com/stnolting/neo430/blob/master/LICENSE)
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[](https://github.com/stnolting/neo430/blob/master/LICENSE)
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[](https://github.com/stnolting/neo430/releases)
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[](https://github.com/stnolting/neo430/releases)
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[](https://raw.githubusercontent.com/stnolting/neo430/master/doc/NEO430.pdf)
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[](https://raw.githubusercontent.com/stnolting/neo430/master/doc/NEO430.pdf)
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[](https://github.com/stnolting/neo430/issues)
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[](https://github.com/stnolting/neo430/issues)
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[](https://github.com/stnolting/neo430/pulls)
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[](https://github.com/stnolting/neo430/pulls)
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[](https://github.com/stnolting/neo430/commits/master)
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[](https://github.com/stnolting/neo430/commits/master)
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## Table of Content
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## Table of Content
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* [Introduction](#Introduction)
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* [Introduction](#Introduction)
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* [Processor Features](#Processor-Features)
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* [Processor Features](#Processor-Features)
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* [Differences to the Original MSP430 Processors](#Differences-to-the-Original-MSP430-Processors)
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* [Differences to the Original MSP430 Processors](#Differences-to-the-Original-MSP430-Processors)
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* [Top Entity](#Top-Entity)
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* [Top Entity](#Top-Entity)
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* [FPGA Implementation Results](#FPGA-Implementation-Results)
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* [FPGA Implementation Results](#FPGA-Implementation-Results)
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* [HW-SW Ecosystem](#HW-SW-Ecosystem)
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* [HW-SW Ecosystem](#HW-SW-Ecosystem)
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* [Performance](#Performance)
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* [Performance](#Performance)
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* [**Quick Start**](#Quick-Start)
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* [**Quick Start**](#Quick-Start)
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* [Change Log](#Change-Log)
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* [Change Log](#Change-Log)
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* [Contact](#Contact)
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* [Contact](#Contact)
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* [Disclaimer, Proprietary and Legal Notice](#Disclaimer-Proprietary-and-Legal-Notice)
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* [Disclaimer, Proprietary and Legal Notice](#Disclaimer-Proprietary-and-Legal-Notice)
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## Introduction
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## Introduction
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Welcome to __[The NEO430 Processor](https://github.com/stnolting/neo430)__ project!
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Welcome to __[The NEO430 Processor](https://github.com/stnolting/neo430)__ project!
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You need a small but still powerful, customizable and microcontroller-like processor system for your next FPGA project?
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You need a small but still powerful, customizable and microcontroller-like processor system for your next FPGA project?
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Then the NEO430 is the right choice for you.
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Then the NEO430 is the right choice for you.
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This processor is based on the Texas Instruments MSP430(TM) ISA and provides compatibility with the original
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This processor is based on the Texas Instruments MSP430(TM) ISA and provides compatibility with the original
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instruction set (see differences below). The NEO430 is not an exact MSP430 clone – it is more like a complete new implementation from the bottom up. The
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instruction set (see differences below). The NEO430 is not an exact MSP430 clone – it is more like a complete new implementation from the bottom up. The
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processor features a very small outline, already implementing standard features like a timer, a watchdog, UART, TWI and SPI
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processor features a very small outline, already implementing standard features like a timer, a watchdog, UART, TWI and SPI
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serial interfaces, general purpose IO ports, an internal bootloader and of course internal memory for program code and data.
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serial interfaces, general purpose IO ports, an internal bootloader and of course internal memory for program code and data.
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All of the implemented peripheral modules are optional – so if you do not need them, you can exclude them from synthesis to
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All of the implemented peripheral modules are optional – so if you do not need them, you can exclude them from synthesis to
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reduce the size of the system. Any additional modules, which make a more customized system, can be connected via a
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reduce the size of the system. Any additional modules, which make a more customized system, can be connected via a
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Wishbone-compatible bus interface or directly implemented within the processor. By this, you can built a system,
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Wishbone-compatible bus interface or directly implemented within the processor. By this, you can built a system,
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that perfectly fits your needs.
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that perfectly fits your needs.
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It is up to you to use the NEO430 as stand-alone, configurable and extensible microcontroller, or to use it as controller
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It is up to you to use the NEO430 as stand-alone, configurable and extensible microcontroller, or to use it as controller
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within a more complex SoC design.
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within a more complex SoC design.
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The high-level software development is based on the free TI msp430-gcc compiler tool chain. You can either use Windows
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The high-level software development is based on the free TI msp430-gcc compiler tool chain. You can either use Windows
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(PowerShell or Linux Subsystem) or Linux as build environment for your applications – the project supports both worlds.
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(PowerShell or Linux Subsystem) or Linux as build environment for your applications – the project supports both worlds.
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This project is intended to work "out of the box". Just synthesize the test setup from this project, upload it to your
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This project is intended to work "out of the box". Just synthesize the test setup from this project, upload it to your
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FPGA board of choice (the NEO430 uses a FPGA vendor-independent VHDL description) and start exploring the capabilities of
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FPGA board of choice (the NEO430 uses a FPGA vendor-independent VHDL description) and start exploring the capabilities of
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the NEO430 processor. Application program generation works by executing a single "make" command. Jump to the
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the NEO430 processor. Application program generation works by executing a single "make" command. Jump to the
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"Let’s Get It Started" chapter in the NEO430 documentary, which provides a lot of guides and tutorials to make your first
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"Let’s Get It Started" chapter in the NEO430 documentary, which provides a lot of guides and tutorials to make your first
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NEO430 setup run: [ NEO430 Datasheet](https://raw.githubusercontent.com/stnolting/neo430/master/doc/NEO430.pdf "NEO430 Datasheet from GitHub")
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NEO430 setup run: [ NEO430 Datasheet](https://raw.githubusercontent.com/stnolting/neo430/master/doc/NEO430.pdf "NEO430 Datasheet from GitHub")
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## Processor Features
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## Processor Features
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(optional modules are marked using dashed lines in the figure above)
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(optional modules are marked using dashed lines in the figure above)
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- 16-bit open source soft-core microcontroller-like processor system
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- 16-bit open source soft-core microcontroller-like processor system
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- Full support of the original [MSP430 instruction set architecture](https://raw.githubusercontent.com/stnolting/neo430/master/doc/instruction_set.pdf)
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- Full support of the original [MSP430 instruction set architecture](https://raw.githubusercontent.com/stnolting/neo430/master/doc/instruction_set.pdf)
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- Code-efficient CISC-like instruction capabilities
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- Code-efficient CISC-like instruction capabilities
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- Tool chain based on free [TI msp430-gcc compiler](http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/latest/index_FDS.html "TI `msp430-gcc` compiler") (also available [here on github](https://github.com/stnolting/msp430-gcc))
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- Tool chain based on free [TI msp430-gcc compiler](http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/latest/index_FDS.html "TI `msp430-gcc` compiler") (also available [here on github](https://github.com/stnolting/msp430-gcc))
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- Application compilation scripts ([makefiles](https://github.com/stnolting/neo430/blob/master/sw/example/blink_led/Makefile)) for Windows Powershell / Windows Subsystem for Linux / native Linux
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- Application compilation scripts ([makefiles](https://github.com/stnolting/neo430/blob/master/sw/example/blink_led/Makefile)) for Windows Powershell / Windows Subsystem for Linux / native Linux
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- Software requirements (regardless of platform):
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- Software requirements (regardless of platform):
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- TI `msp430-gcc` compiler
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- TI `msp430-gcc` compiler
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- native `GCC` compiler
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- native `GCC` compiler
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- `GNU Make`
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- `GNU Make`
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- Completely described in behavioral, platform-independent VHDL (no macros, primitives, attributes, etc. used)
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- Completely described in behavioral, platform-independent VHDL (no macros, primitives, attributes, etc. used)
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- Fully synchronous design, no latches, no gated clocks
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- Fully synchronous design, no latches, no gated clocks
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- Very low resource requirements and high operating frequency
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- Very low resource requirements and high operating frequency
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- Internal [DMEM](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_dmem.vhd) (RAM, for data) and [IMEM](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_imem.vhd) (RAM or ROM, for code), configurable sizes
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- Internal [DMEM](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_dmem.vhd) (RAM, for data) and [IMEM](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_imem.vhd) (RAM or ROM, for code), configurable sizes
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- Customizable processor hardware configuration:
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- Customizable processor hardware configuration:
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- Optional multiplier/divider unit ([MULDIV](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_muldiv.vhd))
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- Optional multiplier/divider unit ([MULDIV](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_muldiv.vhd))
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- Optional high-precision timer ([TIMER](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_timer.vhd))
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- Optional high-precision timer ([TIMER](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_timer.vhd))
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- Optional universal asynchronous receiver and transmitter ([UART](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_uart.vhd))
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- Optional universal asynchronous receiver and transmitter ([UART](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_uart.vhd))
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- Optional serial peripheral interface master ([SPI](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_spi.vhd)), 8 or 16 bit transfer data size, 6 dedicated chip-select lines
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- Optional serial peripheral interface master ([SPI](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_spi.vhd)), 8 or 16 bit transfer data size, 6 dedicated chip-select lines
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- Optional I2C-compatible two wire serial interface master ([TWI](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_twi.vhd)) supporting clock stretching
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- Optional I2C-compatible two wire serial interface master ([TWI](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_twi.vhd)) supporting clock stretching
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- Optional general purpose parallel IO port ([GPIO](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_gpio.vhd)), 16 inputs & 16 outputs, with pin-change interrupt and PWM option
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- Optional general purpose parallel IO port ([GPIO](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_gpio.vhd)), 16 inputs & 16 outputs, with pin-change interrupt and PWM option
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- Optional 32-bit Wishbone bus master interface adapter ([WB32](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_wb_interface.vhd)) - including bridges to [Avalon (TM](https://github.com/stnolting/neo430/blob/master/rtl/top_templates/neo430_top_avm.vhd)) bus and [AXI4-Lite (TM](https://github.com/stnolting/neo430/blob/master/rtl/top_templates/neo430_top_axi4lite.vhd))
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- Optional 32-bit Wishbone bus master interface adapter ([WB32](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_wb_interface.vhd)) - including bridges to [Avalon (TM](https://github.com/stnolting/neo430/blob/master/rtl/top_templates/neo430_top_avm.vhd)) bus and [AXI4-Lite (TM](https://github.com/stnolting/neo430/blob/master/rtl/top_templates/neo430_top_axi4lite.vhd))
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- Optional watchdog timer ([WDT](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_wdt.vhd))
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- Optional watchdog timer ([WDT](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_wdt.vhd))
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- Optional cyclic redundancy check unit ([CRC16/32](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_crc.vhd))
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- Optional cyclic redundancy check unit ([CRC16/32](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_crc.vhd))
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- Optional custom functions unit ([CFU](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_cfu.vhd)) for processor-internal user-defined processor extensions
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- Optional custom functions unit ([CFU](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_cfu.vhd)) for processor-internal user-defined processor extensions
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- Optional 4 channel PWM controller with 4 or 8 bit resolution ([PWM](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_pwm.vhd))
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- Optional 4 channel PWM controller with 4 or 8 bit resolution ([PWM](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_pwm.vhd))
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- Optional Galois Ring Oscillator (GARO) based true random number generator ([TRNG](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_trng.vhd)) with de-biasing and internal post-processing
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- Optional Galois Ring Oscillator (GARO) based true random number generator ([TRNG](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_trng.vhd)) with de-biasing and internal post-processing
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- Optional external interrupts controller with 8 independent channels ([EXIRQ](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_exirq.vhd)), can also be used for software-triggered interrupts (traps, breakpoints, etc.)
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- Optional external interrupts controller with 8 independent channels ([EXIRQ](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_exirq.vhd)), can also be used for software-triggered interrupts (traps, breakpoints, etc.)
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- Optional NCO-based programmable frequency generator ([FREQ_GEN](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_freq_gen.vhd)) with 3 independent output channels
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- Optional NCO-based programmable frequency generator ([FREQ_GEN](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_freq_gen.vhd)) with 3 independent output channels
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- Optional internal [bootloader](https://github.com/stnolting/neo430/blob/master/sw/bootloader/bootloader.c) (2kB ROM) with serial user console and automatic application boot from external SPI flash (like the FPGA configuration storage)
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- Optional internal [bootloader](https://github.com/stnolting/neo430/blob/master/sw/bootloader/bootloader.c) (2kB ROM) with serial user console and automatic application boot from external SPI flash (like the FPGA configuration storage)
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## Differences to the Original MSP430 Processors
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## Differences to the Original MSP430 Processors
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- Completely different processor modules with different functionality
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- Completely different processor modules with different functionality
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- Up to 48kB instruction memory and 12kB data memory
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- Up to 48kB instruction memory and 12kB data memory
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- NEO430 tool chain (makefiles, boot-code and linker script) required for application compilation
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- NEO430 tool chain (makefiles, boot-code and linker script) required for application compilation
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- Custom binary executable format
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- Custom binary executable format
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- No hardware debugging interface
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- No hardware debugging interface
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- No analog components
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- No analog components
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- No support of TI's Code Composer Studio
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- No support of TI's Code Composer Studio
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- No support of CPU's DADD operation
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- No support of CPU's DADD operation
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- _Implicit_ software support of the NEO430 multiplier only via experimental ABI-override mode**
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- _Implicit_ software support of the NEO430 multiplier only via experimental ABI-override mode**
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- Just 4 CPU interrupt channels (can be extended via the external IRQ controller)
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- Just 4 CPU interrupt channels (can be extended via the external IRQ controller)
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- Single clock domain for complete processor
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- Single clock domain for complete processor
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- Different numbers of instruction execution cycles
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- Different numbers of instruction execution cycles
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- Only one power-down (sleep) mode
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- Only one power-down (sleep) mode
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**) A quite promising experimental mode to allow implicit multiplier usage (just write A*B in your code and the compiler
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**) A quite promising experimental mode to allow implicit multiplier usage (just write A*B in your code and the compiler
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will automatically utilize the multiplier unit for this)
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will automatically utilize the multiplier unit for this)
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## Top Entity
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## Top Entity
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The top entity of the processor is [**neo430_top.vhd**](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_top.vhd) (from the rtl\core folder).
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The top entity of the processor is [**neo430_top.vhd**](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_top.vhd) (from the rtl\core folder).
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Just instantiate this file in your project and you are ready to go! All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively.
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Just instantiate this file in your project and you are ready to go! All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively.
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If you need a top entity with resolved signals (*std_logic*), take a look at the [top_templates](https://github.com/stnolting/neo430/blob/master/rtl/top_templates) folder.
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If you need a top entity with resolved signals (*std_logic*), take a look at the [top_templates](https://github.com/stnolting/neo430/blob/master/rtl/top_templates) folder.
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These alternative top entities also support AXI or Avalon connectivity.
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These alternative top entities also support AXI or Avalon connectivity.
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### Generics
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### Generics
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The main features and the actually implemented peripheral modules are configured via the top unit's generics.
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The main features and the actually implemented peripheral modules are configured via the top unit's generics.
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| Generic Name | Type | Default Value | Function |
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| Generic Name | Type | Default Value | Function |
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|:-------------|:-----------------------:|:-------------:|:---------------------------------------------------------|
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|:-------------|:-----------------------:|:-------------:|:---------------------------------------------------------|
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| CLOCK_SPEED | natural | 100000000 | Clock speed of CPU clock input "clk_i" in Hz |
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| CLOCK_SPEED | natural | 100000000 | Clock speed of CPU clock input "clk_i" in Hz |
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| IMEM_SIZE | natural | 4*1024 | Size of internal instruction memory in bytes (max 48 kB) |
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| IMEM_SIZE | natural | 4*1024 | Size of internal instruction memory in bytes (max 48 kB) |
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| DMEM_SIZE | natural | 2*1024 | Size of internal data memory in bytes (max 12 kB) |
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| DMEM_SIZE | natural | 2*1024 | Size of internal data memory in bytes (max 12 kB) |
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| USER_CODE | std_ulogic_vector(15:0) | x"0000" | 16-bit custom user code, can be read by user software |
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| USER_CODE | std_ulogic_vector(15:0) | x"0000" | 16-bit custom user code, can be read by user software |
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| MULDIV_USE | boolean | true | Implement multiplier/divider unit (MULDIV) |
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| MULDIV_USE | boolean | true | Implement multiplier/divider unit (MULDIV) |
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| WB32_USE | boolean | true | Implement Wishbone interface adapter (WB32) |
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| WB32_USE | boolean | true | Implement Wishbone interface adapter (WB32) |
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| WDT_USE | boolean | true | Implement watchdog timer (WDT) |
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| WDT_USE | boolean | true | Implement watchdog timer (WDT) |
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| GPIO_USE | boolean | true | Implement general purpose parallel in/out port (GPIO) |
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| GPIO_USE | boolean | true | Implement general purpose parallel in/out port (GPIO) |
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| TIMER_USE | boolean | true | Implement high-precision timer (TIMER) |
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| TIMER_USE | boolean | true | Implement high-precision timer (TIMER) |
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| UART_USE | boolean | true | Implement UART serial communication unit (UART) |
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| UART_USE | boolean | true | Implement UART serial communication unit (UART) |
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| CRC_USE | boolean | true | Implement checksum computation unit (CRC16/32) |
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| CRC_USE | boolean | true | Implement checksum computation unit (CRC16/32) |
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| CFU_USE | boolean | false | Implement custom functions unit (CFU) |
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| CFU_USE | boolean | false | Implement custom functions unit (CFU) |
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| PWM_USE | boolean | true | Implement pulse width controller (PWM) |
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| PWM_USE | boolean | true | Implement pulse width controller (PWM) |
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| TWI_USE | boolean | true | Implement two wire serial interface unit (TWI) |
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| TWI_USE | boolean | true | Implement two wire serial interface unit (TWI) |
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| SPI_USE | boolean | true | Implement serial peripheral interface unit (SPI) |
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| SPI_USE | boolean | true | Implement serial peripheral interface unit (SPI) |
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| TRNG_USE | boolean | false | Implement true random number generator (TRNG) |
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| TRNG_USE | boolean | false | Implement true random number generator (TRNG) |
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| EXIRQ_USE | boolean | true | Implement external interrupts controller (EXIRQ) |
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| EXIRQ_USE | boolean | true | Implement external interrupts controller (EXIRQ) |
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| FREQ_GEN_USE | boolean | true | Implement programmable frequency generator (FREQ_GEN) |
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| FREQ_GEN_USE | boolean | true | Implement programmable frequency generator (FREQ_GEN) |
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| BOOTLD_USE | boolean | true | Implement and auto-start internal bootloader |
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| BOOTLD_USE | boolean | true | Implement and auto-start internal bootloader |
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| IMEM_AS_ROM | boolean | false | Implement internal instruction memory as read-only |
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| IMEM_AS_ROM | boolean | false | Implement internal instruction memory as read-only |
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### Signals
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### Signals
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Regarding unused unit's signals: Connect all unused inputs to low and leave all unused outputs 'open'.
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Regarding unused unit's signals: Connect all unused inputs to low and leave all unused outputs 'open'.
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Signal driections are seen from the processor.
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Signal driections are seen from the processor.
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| Signal Name | Width | Direction | HW Unit | Function |
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| Signal Name | Width | Direction | HW Unit | Function |
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|:-------------|:-----:|:---------:|:--------:|:---------------------------------------------------------|
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|:-------------|:-----:|:---------:|:--------:|:---------------------------------------------------------|
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| clk_i | 1 | In | - | Global clock line; all FFs triggering on rising edge |
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| clk_i | 1 | In | - | Global clock line; all FFs triggering on rising edge |
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| rst_i | 1 | In | - | Global reset, low-active |
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| rst_i | 1 | In | - | Global reset, low-active |
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| gpio_o | 16 | Out | GPIO | General purpose parallel output |
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| gpio_o | 16 | Out | GPIO | General purpose parallel output |
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| gpio_i | 16 | In | GPIO | General purpose parallel input |
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| gpio_i | 16 | In | GPIO | General purpose parallel input |
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| pwm_o | 4 | Out | PWM | Pulse width modulation channels |
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| pwm_o | 4 | Out | PWM | Pulse width modulation channels |
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| timer_fg_o | 1 | Out | FREQ_GEN | Programmable frequency generator output |
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| timer_fg_o | 1 | Out | FREQ_GEN | Programmable frequency generator output |
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| uart_txd_o | 1 | Out | UART | UART serial transmitter |
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| uart_txd_o | 1 | Out | UART | UART serial transmitter |
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| uart_rxd_i | 1 | In | UART | UARt serial receiver |
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| uart_rxd_i | 1 | In | UART | UARt serial receiver |
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| spi_sclk_o | 1 | Out | SPI | SPI master clock |
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| spi_sclk_o | 1 | Out | SPI | SPI master clock |
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| spi_mosi_o | 1 | Out | SPI | SPI serial data output |
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| spi_mosi_o | 1 | Out | SPI | SPI serial data output |
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| spi_miso_i | 1 | In | SPI | SPI serial data input |
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| spi_miso_i | 1 | In | SPI | SPI serial data input |
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| spi_cs_o | 8 | Out | SPI | SPI chip select lines (active-low) |
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| spi_cs_o | 8 | Out | SPI | SPI chip select lines (active-low) |
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| twi_sda_io | 1 | InOut | TWI | TWI master serial data line (external pull-up required) |
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| twi_sda_io | 1 | InOut | TWI | TWI master serial data line (external pull-up required) |
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| twi_scl_io | 1 | InOut | TWI | TWI master serial clock line (external pull-up required) |
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| twi_scl_io | 1 | InOut | TWI | TWI master serial clock line (external pull-up required) |
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| wb_adr_o | 32 | Out | WB32 | Wishbone slave address |
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| wb_adr_o | 32 | Out | WB32 | Wishbone slave address |
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| wb_dat_i | 32 | In | WB32 | Wishbone write data |
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| wb_dat_i | 32 | In | WB32 | Wishbone write data |
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| wb_dat_o | 32 | Out | WB32 | Wishbone read data |
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| wb_dat_o | 32 | Out | WB32 | Wishbone read data |
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| wb_we_o | 1 | Out | WB32 | Wishbone write enable |
|
| wb_we_o | 1 | Out | WB32 | Wishbone write enable |
|
| wb_sel_o | 1 | Out | WB32 | Wishbone byte enable |
|
| wb_sel_o | 1 | Out | WB32 | Wishbone byte enable |
|
| wb_stb_o | 1 | Out | WB32 | Wishbone strobe |
|
| wb_stb_o | 1 | Out | WB32 | Wishbone strobe |
|
| wb_cyc_o | 1 | Out | WB32 | Wishbone valid cycle |
|
| wb_cyc_o | 1 | Out | WB32 | Wishbone valid cycle |
|
| wb_ack_i | 1 | In | WB32 | Wishbone transfer acknowledge |
|
| wb_ack_i | 1 | In | WB32 | Wishbone transfer acknowledge |
|
| ext_irq_i | 8 | In | EXIRQ | Interrupt request lines, high-active |
|
| ext_irq_i | 8 | In | EXIRQ | Interrupt request lines, high-active |
|
| ext_ack_o | 8 | Out | EXIRQ | Interrupt acknowledge, high-active, single-shot |
|
| ext_ack_o | 8 | Out | EXIRQ | Interrupt acknowledge, high-active, single-shot |
|
|
|
|
|
|
|
## FPGA Implementation Results
|
## FPGA Implementation Results
|
|
|
Mapping results generated for HW version 0x0406. The full (default) hardware configuration includes
|
Mapping results generated for HW version 0x0406. The full (default) hardware configuration includes
|
all optional processor modules (excluding the CFU and the TRNG), an IMEM size of 4kB and a DMEM
|
all optional processor modules (excluding the CFU and the TRNG), an IMEM size of 4kB and a DMEM
|
size of 2kB. The minimal configuration only includes the CPU (including IMEM and DMEM) and the GPIO module.
|
size of 2kB. The minimal configuration only includes the CPU (including IMEM and DMEM) and the GPIO module.
|
Results generated with Xilinx Vivado 2019.2, Intel Quartus Prime Lite 17.1 and Lattice Radiant 1.1 (Synplify)
|
Results generated with Xilinx Vivado 2019.2, Intel Quartus Prime Lite 17.1 and Lattice Radiant 1.1 (Synplify)
|
|
|
| __Xilinx Artix-7 (XC7A35TICSG324-1L)__ | LUTs | FFs | BRAMs | DSPs | f_max* |
|
| __Xilinx Artix-7 (XC7A35TICSG324-1L)__ | LUTs | FFs | BRAMs | DSPs | f_max* |
|
|:---------------------------------------|:---------:|:------------:|:--------:|:------:|:-------:|
|
|:---------------------------------------|:---------:|:------------:|:--------:|:------:|:-------:|
|
| Full (default) configuration: | 1036 (5%) | 1144 (2.75%) | 2.5 (5%) | 0 (0%) | 100 MHz |
|
| Full (default) configuration: | 1036 (5%) | 1144 (2.75%) | 2.5 (5%) | 0 (0%) | 100 MHz |
|
| Minimal configuration (CPU + GPIO): | 576 (3%) | 266 (0.6%) | 1 (2%) | 0 (0%) | 100 MHz |
|
| Minimal configuration (CPU + GPIO): | 576 (3%) | 266 (0.6%) | 1 (2%) | 0 (0%) | 100 MHz |
|
|
|
| __Intel Cyclone IV (EP4CE22F17C6)__ | LUTs | FFs | Memory bits | DSPs | f_max |
|
| __Intel Cyclone IV (EP4CE22F17C6)__ | LUTs | FFs | Memory bits | DSPs | f_max |
|
|:------------------------------------|:---------:|:---------:|:-----------:|:------:|:-------:|
|
|:------------------------------------|:---------:|:---------:|:-----------:|:------:|:-------:|
|
| Full (default) configuration: | 1869 (8%) | 1137 (5%) | 65800 (11%) | 0 (0%) | 121 MHz |
|
| Full (default) configuration: | 1869 (8%) | 1137 (5%) | 65800 (11%) | 0 (0%) | 121 MHz |
|
| Minimal configuration (CPU + GPIO): | 590 (3%) | 230 (1%) | 49408 (8%) | 0 (0%) | 122 MHz |
|
| Minimal configuration (CPU + GPIO): | 590 (3%) | 230 (1%) | 49408 (8%) | 0 (0%) | 122 MHz |
|
|
|
| __Lattice iCE40 UltraPlus** (iCE40UP5K-SG48I)__ | LUTs | FFs | EBRs | DSPs | SPRAMs | f_max* |
|
| __Lattice iCE40 UltraPlus** (iCE40UP5K-SG48I)__ | LUTs | FFs | EBRs | DSPs | SPRAMs | f_max* |
|
|:-------------------------------------------------|:----------:|:----------:|:-------:|:------:|:-------:|:---------:|
|
|:-------------------------------------------------|:----------:|:----------:|:-------:|:------:|:-------:|:---------:|
|
| Full (default) configuration: | 3928 (74%) | 1923 (36%) | 9 (30%) | 0 (0%) | 2 (50%) | 20.25 MHz |
|
| Full (default) configuration: | 3928 (74%) | 1923 (36%) | 9 (30%) | 0 (0%) | 2 (50%) | 20.25 MHz |
|
| Minimal configuration (CPU + GPIO + Bootloader): | 1812 (34%) | 755 (14%) | 4 (13%) | 0 (0%) | 2 (50%) | 20.25 MHz |
|
| Minimal configuration (CPU + GPIO + Bootloader): | 1812 (34%) | 755 (14%) | 4 (13%) | 0 (0%) | 2 (50%) | 20.25 MHz |
|
|
|
*) Constrained
|
*) Constrained
|
|
|
**) Using optimized memory modules for IMEM (32kB) & DMEM (12kB) from the `rtl\fpga_specific\lattice_ice40up` folder
|
**) Using optimized memory modules for IMEM (32kB) & DMEM (12kB) from the `rtl\fpga_specific\lattice_ice40up` folder
|
|
|
|
|
### Device Utilization by Entity
|
### Device Utilization by Entity
|
|
|
The following table shows the required resources for each module of the NEO430 processor system. Note that the provided
|
The following table shows the required resources for each module of the NEO430 processor system. Note that the provided
|
numbers only represent a coarse overview as logic elements might be merged and optimized beyond entity boundaries.
|
numbers only represent a coarse overview as logic elements might be merged and optimized beyond entity boundaries.
|
|
|
Mapping results generated for HW version 0x0406. The full (default) hardware configuration includes all optional
|
Mapping results generated for HW version 0x0406. The full (default) hardware configuration includes all optional
|
processor modules (excluding the CFU but including the TRNG), an IMEM size of 4kB and a DMEM size of
|
processor modules (excluding the CFU but including the TRNG), an IMEM size of 4kB and a DMEM size of
|
2kB. Results were generated using Intel Quartus Prime Lite 17.1.
|
2kB. Results were generated using Intel Quartus Prime Lite 17.1.
|
|
|
| __Intel Cyclone IV (EP4CE22F17C6)__ | LUTs | FFs | Memory Bits | DSPs |
|
| __Intel Cyclone IV (EP4CE22F17C6)__ | LUTs | FFs | Memory Bits | DSPs |
|
|:---------------------------------------|:----:|:---:|:-----------:|:----:|
|
|:---------------------------------------|:----:|:---:|:-----------:|:----:|
|
| Bootloader Memory (Boot ROM, 2kB) | 2 | 1 | 16384 | 0 |
|
| Bootloader Memory (Boot ROM, 2kB) | 2 | 1 | 16384 | 0 |
|
| Central Processing Unit (CPU) | 525 | 169 | 264 | 0 |
|
| Central Processing Unit (CPU) | 525 | 169 | 264 | 0 |
|
| Checksum Unit (CRC) | 111 | 94 | 0 | 0 |
|
| Checksum Unit (CRC) | 111 | 94 | 0 | 0 |
|
| Custom Functions Unit (CFU)* | - | - | - | - |
|
| Custom Functions Unit (CFU)* | - | - | - | - |
|
| Data Memory (DMEM, 2kB) | 5 | 1 | 16384 | 0 |
|
| Data Memory (DMEM, 2kB) | 5 | 1 | 16384 | 0 |
|
| External Interrupts Controller (EXIRQ) | 70 | 55 | 0 | 0 |
|
| External Interrupts Controller (EXIRQ) | 70 | 55 | 0 | 0 |
|
| Frequency Generator (FREQ_GEN) | 140 | 130 | 0 | 0 |
|
| Frequency Generator (FREQ_GEN) | 140 | 130 | 0 | 0 |
|
| GPIO Port Unit (GPIO) | 50 | 45 | 0 | 0 |
|
| GPIO Port Unit (GPIO) | 50 | 45 | 0 | 0 |
|
| High-Precision Timer (TIMER) | 66 | 57 | 0 | 0 |
|
| High-Precision Timer (TIMER) | 66 | 57 | 0 | 0 |
|
| Instruction Memory (IMEM, 4kB) | 5 | 1 | 32768 | 0 |
|
| Instruction Memory (IMEM, 4kB) | 5 | 1 | 32768 | 0 |
|
| Multiplier & Divider (MULDIV) | 209 | 134 | 0 | 0 |
|
| Multiplier & Divider (MULDIV) | 209 | 134 | 0 | 0 |
|
| Pulse-Width Modulation Unit (PWM) | 96 | 66 | 0 | 0 |
|
| Pulse-Width Modulation Unit (PWM) | 96 | 66 | 0 | 0 |
|
| Serial Peripheral Interface (SPI) | 82 | 59 | 0 | 0 |
|
| Serial Peripheral Interface (SPI) | 82 | 59 | 0 | 0 |
|
| System Info Memory (SYSCONFIG) | 12 | 11 | 0 | 0 |
|
| System Info Memory (SYSCONFIG) | 12 | 11 | 0 | 0 |
|
| True Random Number Generator (TRNG) | 92 | 76 | 0 | 0 |
|
| True Random Number Generator (TRNG) | 92 | 76 | 0 | 0 |
|
| Two Wire Interface (TWI) | 78 | 43 | 0 | 0 |
|
| Two Wire Interface (TWI) | 78 | 43 | 0 | 0 |
|
| Universal Asynchronous Rx/Tx (UART) | 130 | 91 | 0 | 0 |
|
| Universal Asynchronous Rx/Tx (UART) | 130 | 91 | 0 | 0 |
|
| Watchdog Timer (WDT) | 53 | 37 | 0 | 0 |
|
| Watchdog Timer (WDT) | 53 | 37 | 0 | 0 |
|
| Wishbone Interface (WB32) | 129 | 117 | 0 | 0 |
|
| Wishbone Interface (WB32) | 129 | 117 | 0 | 0 |
|
|
|
*) Hardware requirements defined by user application
|
*) Hardware requirements defined by user application
|
|
|
|
|
|
|
## HW-SW Ecosystem
|
## HW-SW Ecosystem
|
|
|
The NEO430 Processor project provides driver libraries for the CPU itself and all included peripheral modules. These libraries
|
The NEO430 Processor project provides driver libraries for the CPU itself and all included peripheral modules. These libraries
|
provide a certain level of hardware abstraction and allow an easy usage of the different hardware modules. Modules that cannot
|
provide a certain level of hardware abstraction and allow an easy usage of the different hardware modules. Modules that cannot
|
be used "explicitly" (like CPU modules or the different memories) are not listed below.
|
be used "explicitly" (like CPU modules or the different memories) are not listed below.
|
|
|
| Hardware unit | VHDL source | C library source | C library header | SW example project |
|
| Hardware unit | VHDL source | C library source | C library header | SW example project |
|
|:---------------------------------------|:-----------:|:----------------:|:----------------:|:------------------:|
|
|:---------------------------------------|:-----------:|:----------------:|:----------------:|:------------------:|
|
| Main CPU defines file | - | - | [neo430.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430.h) | - |
|
| Main CPU defines file | - | - | [neo430.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430.h) | - |
|
| Central Processing Unit (CPU) | [neo430_cpu.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_cpu.vhd) | [neo430_cpu.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_cpu.c) | [neo430_cpu.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_cpu.h) |- |
|
| Central Processing Unit (CPU) | [neo430_cpu.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_cpu.vhd) | [neo430_cpu.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_cpu.c) | [neo430_cpu.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_cpu.h) |- |
|
| Custom Functions Unit (CFU) | [neo430_cfu.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_cfu.vhd) | provided by CFU designer | provided by CFU designer | [example](https://github.com/stnolting/neo430/tree/master/sw/example/cfu_test) |
|
| Custom Functions Unit (CFU) | [neo430_cfu.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_cfu.vhd) | provided by CFU designer | provided by CFU designer | [example](https://github.com/stnolting/neo430/tree/master/sw/example/cfu_test) |
|
| Checksum Unit (CRC16/32) | [neo430_crc.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_crc.vhd) | [neo430_crc.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_crc.c) | [neo430_crc.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_crc.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/example/crc_test) |
|
| Checksum Unit (CRC16/32) | [neo430_crc.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_crc.vhd) | [neo430_crc.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_crc.c) | [neo430_crc.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_crc.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/example/crc_test) |
|
| External Interrupts Controller (EXIRQ) | [neo430_exirq.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_exirq.vhd) | [neo430_exirq.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_exirq.c) | [neo430_exirq.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_exirq.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/example/exirq_test) |
|
| External Interrupts Controller (EXIRQ) | [neo430_exirq.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_exirq.vhd) | [neo430_exirq.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_exirq.c) | [neo430_exirq.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_exirq.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/example/exirq_test) |
|
| Frequency Generator (FREQ_GEN) | [neo430_freq_gen.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_freq_gen.vhd) | [neo430_freq_gen.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_freq_gen.c) | [neo430_freq_gen.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_freq_gen.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/example/freq_gen_demo) |
|
| Frequency Generator (FREQ_GEN) | [neo430_freq_gen.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_freq_gen.vhd) | [neo430_freq_gen.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_freq_gen.c) | [neo430_freq_gen.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_freq_gen.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/example/freq_gen_demo) |
|
| IO Port Unit (GPIO) | [neo430_gpio.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_gpio.vhd) | [neo430_gpio.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_gpio.c) | [neo430_gpio.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_gpio.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/example/blink_led) |
|
| IO Port Unit (GPIO) | [neo430_gpio.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_gpio.vhd) | [neo430_gpio.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_gpio.c) | [neo430_gpio.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_gpio.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/example/blink_led) |
|
| Multiplier & Divider (MULDIV) | [neo430_muldiv.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_muldiv.vhd) | [neo430_muldiv.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_muldiv.c) | [neo430_muldiv.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_muldiv.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/example/muldiv_test) |
|
| Multiplier & Divider (MULDIV) | [neo430_muldiv.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_muldiv.vhd) | [neo430_muldiv.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_muldiv.c) | [neo430_muldiv.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_muldiv.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/example/muldiv_test) |
|
| Pulse-Width Modulation Unit (PWM) | [neo430_pwm.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_pwm.vhd) | [neo430_pwm.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_pwm.c) | [neo430_pwm.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_pwm.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/example/pwm_demo) |
|
| Pulse-Width Modulation Unit (PWM) | [neo430_pwm.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_pwm.vhd) | [neo430_pwm.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_pwm.c) | [neo430_pwm.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_pwm.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/example/pwm_demo) |
|
| Serial Peripheral Interface (SPI) | [neo430_spi.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_spi.vhd) | [neo430_spi.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_spi.c) | [neo430_spi.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_spi.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/bootloader) |
|
| Serial Peripheral Interface (SPI) | [neo430_spi.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_spi.vhd) | [neo430_spi.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_spi.c) | [neo430_spi.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_spi.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/bootloader) |
|
| High-Precision Timer (TIMER) | [neo430_timer.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_timer.vhd) | [neo430_timer.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_timer.c) | [neo430_timer.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_timer.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/example/timer_simple) |
|
| High-Precision Timer (TIMER) | [neo430_timer.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_timer.vhd) | [neo430_timer.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_timer.c) | [neo430_timer.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_timer.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/example/timer_simple) |
|
| True Random Number Generator (TRNG) | [neo430_trng.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_trng.vhd) | [neo430_trng.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_trng.c) | [neo430_trng.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_trng.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/example/trng_test) |
|
| True Random Number Generator (TRNG) | [neo430_trng.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_trng.vhd) | [neo430_trng.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_trng.c) | [neo430_trng.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_trng.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/example/trng_test) |
|
| Two Wire Interface (TWI) | [neo430_twi.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_twi.vhd) | [neo430_twi.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_twi.c) | [neo430_twi.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_twi.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/example/twi_test) |
|
| Two Wire Interface (TWI) | [neo430_twi.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_twi.vhd) | [neo430_twi.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_twi.c) | [neo430_twi.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_twi.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/example/twi_test) |
|
| Universal Asynchronous Rx/Tx (UART) | [neo430_uart.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_uart.vhd) | [neo430_uart.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_uart.c) | [neo430_uart.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_uart.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/example/uart_irq) |
|
| Universal Asynchronous Rx/Tx (UART) | [neo430_uart.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_uart.vhd) | [neo430_uart.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_uart.c) | [neo430_uart.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_uart.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/example/uart_irq) |
|
| Watchdog Timer (WDT) | [neo430_wdt.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_wdt.vhd) | [neo430_wdt.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_wdt.c) | [neo430_wdt.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_wdt.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/example/wdt_test) |
|
| Watchdog Timer (WDT) | [neo430_wdt.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_wdt.vhd) | [neo430_wdt.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_wdt.c) | [neo430_wdt.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_wdt.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/example/wdt_test) |
|
| Wishbone Interface (WB32) | [neo430_wb_interface.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_wb_interface.vhd) | [neo430_wishbone.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_wishbone.c) | [neo430_wishbone.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_wishbone.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/example/wb_terminal) |
|
| Wishbone Interface (WB32) | [neo430_wb_interface.vhd](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_wb_interface.vhd) | [neo430_wishbone.c](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/source/neo430_wishbone.c) | [neo430_wishbone.h](https://github.com/stnolting/neo430/blob/master/sw/lib/neo430/include/neo430_wishbone.h) | [example](https://github.com/stnolting/neo430/tree/master/sw/example/wb_terminal) |
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|
|
All software projects are compiled using an [application makefile](https://github.com/stnolting/neo430/blob/master/sw/example/blink_led/makefile).
|
All software projects are compiled using an [application makefile](https://github.com/stnolting/neo430/blob/master/sw/example/blink_led/makefile).
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|
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## Performance
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## Performance
|
|
|
In contrast to most mainstream processors the NEO430 processor does not implement a "classic" pipelined instruction execution. Instead,
|
In contrast to most mainstream processors the NEO430 processor does not implement a "classic" pipelined instruction execution. Instead,
|
a **multi-cycle instruction execution scheme** is used: Each single instruction is executed in a series of micro instructions
|
a **multi-cycle instruction execution scheme** is used: Each single instruction is executed in a series of micro instructions
|
requiring several clock cycles to complete. The main benefit of this execution style is the highly reduced logic overhead as no
|
requiring several clock cycles to complete. The main benefit of this execution style is the highly reduced logic overhead as no
|
complex pipeline hazard detection and resolving logic is required. This makes the NEO430 even smaller - at the cost of a reduced IPC
|
complex pipeline hazard detection and resolving logic is required. This makes the NEO430 even smaller - at the cost of a reduced IPC
|
(*instructions per cycle*). Also, the MSP430 ISA is not really compatible to the classic (DLX/MIPS-like) pipeline scheme due to
|
(*instructions per cycle*). Also, the MSP430 ISA is not really compatible to the classic (DLX/MIPS-like) pipeline scheme due to
|
its complex operand and adressing modes (e.g., ALU operations executing directly on memory data). However, this concept allows
|
its complex operand and adressing modes (e.g., ALU operations executing directly on memory data). However, this concept allows
|
the processor to use very **dense and powerfull CISC-like operations**.
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the processor to use very **dense and powerfull CISC-like operations**.
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|
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Furthermore, the multi-cycle architecture features a **very short crtitical path** when compared to other (even 32-bit)
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Furthermore, the multi-cycle architecture features a **very short crtitical path** when compared to other (even 32-bit)
|
processors. Thus, the NEO430 can operate at very high frequencies even on low-cost (e.g., +120MHz on an Intel Cyclone IV)
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processors. Thus, the NEO430 can operate at very high frequencies even on low-cost (e.g., +120MHz on an Intel Cyclone IV)
|
and low-power FPGAs (e.g., +20MHz on a Lattice iCE40 UltraPlus) even without any area constraints.
|
and low-power FPGAs (e.g., +20MHz on a Lattice iCE40 UltraPlus) even without any area constraints.
|
|
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Depending on the format / operand addressing mode of an instruction, the actual execution can take 3 to 10 clock cycles. If all possible instruction
|
Depending on the format / operand addressing mode of an instruction, the actual execution can take 3 to 10 clock cycles. If all possible instruction
|
types and formats are executed in an equally distributed manner (this is the worst case), the average CPI (clock cycles per instruction)
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types and formats are executed in an equally distributed manner (this is the worst case), the average CPI (clock cycles per instruction)
|
evaluates to **7.33 cycles/instruction resulting in 0.136 MIPS per MHz (again: worst case)**.
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evaluates to **7.33 cycles/instruction resulting in 0.136 MIPS per MHz (again: worst case)**.
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### CoreMark Benchmark
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### CoreMark Benchmark
|
|
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The [CoreMark CPU benchmark](https://www.eembc.org/coremark/) was executed on the NEO430 and is available in the
|
The [CoreMark CPU benchmark](https://www.eembc.org/coremark/) was executed on the NEO430 and is available in the
|
[sw/example/coremark](https://github.com/stnolting/neo430/blob/master/sw/example/coremark) project folder This benchmark
|
[sw/example/coremark](https://github.com/stnolting/neo430/blob/master/sw/example/coremark) project folder This benchmark
|
tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.
|
tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.
|
|
|
~~~
|
~~~
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Configuration
|
Configuration
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Hardware: 100 MHz, 32kB IMEM, 12kB DMEM, HW verison 0x0406, peripherals used: TIMER, UART, MULDIV
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Hardware: 100 MHz, 32kB IMEM, 12kB DMEM, HW verison 0x0407, peripherals used: TIMER, UART, MULDIV
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Software: msp430-gcc 8.3.0 for Linux, MEM_METHOD is MEM_STACK, 2000 CoreMark iterations
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Software: msp430-gcc 8.3.0 for Linux, MEM_METHOD is MEM_STACK, 2000 CoreMark iterations
|
~~~
|
~~~
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|
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| __Optimization/Configuration__ | __Executable Size__ | __CoreMark Score__ | __Relative Score__ |
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| __Optimization/Configuration__ | __Executable Size__ | __CoreMark Score__ | __Relative Score__ |
|
|:-------------------------------|:-------------------:|:------------------:|:-------------------:|
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|:-------------------------------|:-------------------:|:------------------:|:-------------------:|
|
| -Os | 12150 bytes | 6.57 | 0.065 CoreMarks/MHz |
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| -Os | 12150 bytes | 6.57 | 0.065 CoreMarks/MHz |
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| -O2 | 14600 bytes | 7.16 | 0.072 CoreMarks/MHz |
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| -O2 | 14600 bytes | 7.16 | 0.072 CoreMarks/MHz |
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| -Os + NEO430_MULDIV* | 12118 bytes | 14.43 | 0.144 CoreMarks/MHz |
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| -Os + NEO430_MULDIV* | 12118 bytes | 14.43 | 0.144 CoreMarks/MHz |
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| -O2 + NEO430_MULDIV* | 14562 bytes | 17.68 | 0.176 CoreMarks/MHz |
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| -O2 + NEO430_MULDIV* | 14562 bytes | 17.68 | 0.176 CoreMarks/MHz |
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| -Os + NEO430_MULDIV* (DSP**) | 12060 bytes | 15.63 | 0.156 CoreMarks/MHz |
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| -Os + NEO430_MULDIV* (DSP**) | 12060 bytes | 15.63 | 0.156 CoreMarks/MHz |
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| -O2 + NEO430_MULDIV* (DSP**) | 14510 bytes | 19.42 | 0.194 CoreMarks/MHz |
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| -O2 + NEO430_MULDIV* (DSP**) | 14510 bytes | 19.42 | 0.194 CoreMarks/MHz |
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|
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*) These results were generated using the "NEO430_HWMUL_ABI_OVERRIDE" feature flag, which allows to map implicit multiplications
|
*) These results were generated using the "NEO430_HWMUL_ABI_OVERRIDE" feature flag, which allows to map implicit multiplications
|
in the source code via compiler primitives directly to the multiplier core of the MULDIV unit. For more information see
|
in the source code via compiler primitives directly to the multiplier core of the MULDIV unit. For more information see
|
chapter "Multiplier and Divider Unit (MULDIV)" of [NEO430.pdf](https://raw.githubusercontent.com/stnolting/neo430/master/doc/NEO430.pdf).
|
chapter "Multiplier and Divider Unit (MULDIV)" of [NEO430.pdf](https://raw.githubusercontent.com/stnolting/neo430/master/doc/NEO430.pdf).
|
|
|
**) This setup uses the FPGA's embedded multipliers (DSP blocks) for the MULDIV's multiplier unit. The "NEO430_HWMUL_DSP" feature flag eliminates
|
**) This setup uses the FPGA's embedded multipliers (DSP blocks) for the MULDIV's multiplier unit. The "NEO430_HWMUL_DSP" feature flag eliminates
|
the wait cycles usually required to wait for the result generated by the default serial MULDIV multiplier core.
|
the wait cycles usually required to wait for the result generated by the default serial MULDIV multiplier core.
|
|
|
Even though a score of 6.57 can outnumber certain architectures and configurations (see the score table on the CoreMark
|
Even though a score of 6.57 can outnumber certain architectures and configurations (see the score table on the CoreMark
|
homepage), the relative score of 0.065 coremarks per second might sound pretty low. True. But you have to keep in mind that benchmark
|
homepage), the relative score of 0.065 coremarks per second might sound pretty low. True. But you have to keep in mind that benchmark
|
was executed using only the resources of the CPU itself. The CPU consists of only ~520 Intel Cyclone IV LUTs and does not
|
was executed using only the resources of the CPU itself. The CPU consists of only ~520 Intel Cyclone IV LUTs and does not
|
contain any sophisticated ALU operations like multiplication or barrel shifting. When including NEO430 MULDIV unit (using the
|
contain any sophisticated ALU operations like multiplication or barrel shifting. When including NEO430 MULDIV unit (using the
|
"NEO430_HWMUL_ABI_OVERRIDE" feature and using embedded DSP blocks ("NEO430_HWMUL_DSP")) the CoreMark score is increased to 19.42.
|
"NEO430_HWMUL_ABI_OVERRIDE" feature and using embedded DSP blocks ("NEO430_HWMUL_DSP")) the CoreMark score is increased to 19.42.
|
By explicitly using additional HW accelerators from the NEO430 ecosystem (e.g. the CRC unit) the performance can be further increased.
|
By explicitly using additional HW accelerators from the NEO430 ecosystem (e.g. the CRC unit) the performance can be further increased.
|
|
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|
|
|
|
## Quick Start
|
## Quick Start
|
|
|
* At first, get the most recent version the NEO430 Processor project from GitHub:
|
* At first, get the most recent version the NEO430 Processor project from GitHub:
|
|
|
* Clone the NEO430 repository using `git` from the command line (suggested for easy project updates via `git pull`):
|
* Clone the NEO430 repository using `git` from the command line (suggested for easy project updates via `git pull`):
|
|
|
~~~
|
~~~
|
git clone https://github.com/stnolting/neo430.git
|
git clone https://github.com/stnolting/neo430.git
|
~~~
|
~~~
|
|
|
* Or download the current version of this project as ZIP file: [neo430-master.zip](https://github.com/stnolting/neo430/archive/master.zip)
|
* Or download the current version of this project as ZIP file: [neo430-master.zip](https://github.com/stnolting/neo430/archive/master.zip)
|
|
|
* Next, install the free `MSP430-GCC` compiler toolchain from the TI homepage (select the "compiler only" package according to your system OS):
|
* Next, install the free `MSP430-GCC` compiler toolchain from the TI homepage (select the "compiler only" package according to your system OS):
|
|
|
https://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/latest/index_FDS.html
|
https://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/latest/index_FDS.html
|
|
|
* Alternatively, you can [directly download a copy](https://github.com/stnolting/msp430-gcc) of the msp430-gcc toolchain for Windows/Linux from github
|
* Alternatively, you can [directly download a copy](https://github.com/stnolting/msp430-gcc) of the msp430-gcc toolchain for Windows/Linux from github
|
|
|
* Make sure `GNU Make` and a native `GCC` compiler are installed (double check for the newest versions)
|
* Make sure `GNU Make` and a native `GCC` compiler are installed (double check for the newest versions)
|
|
|
* Create a new HW project with your FPGA synthesis tool of choice. Add all files from the `rtl\core` folder to this project (and add them to a new library called "neo430").
|
* Create a new HW project with your FPGA synthesis tool of choice. Add all files from the `rtl\core` folder to this project (and add them to a new library called "neo430").
|
|
|
* Follow the instructions from the "Let's Get It Started" section of the NEO430 documentary: [ NEO430 Datasheet](https://raw.githubusercontent.com/stnolting/neo430/master/doc/NEO430.pdf "NEO430 Datasheet from GitHub")
|
* Follow the instructions from the "Let's Get It Started" section of the NEO430 documentary: [ NEO430 Datasheet](https://raw.githubusercontent.com/stnolting/neo430/master/doc/NEO430.pdf "NEO430 Datasheet from GitHub")
|
|
|
* This documentary will guide you to create a simple test setup, which serves as ["hello word" FPGA demo](https://github.com/stnolting/neo430/blob/master/rtl/top_templates/neo430_test.vhd):
|
* This documentary will guide you to create a simple test setup, which serves as ["hello word" FPGA demo](https://github.com/stnolting/neo430/blob/master/rtl/top_templates/neo430_test.vhd):
|
|
|
|
|
|
|
* The NEO430 project also includes some example programs from which you can start your own application: [SW example projects](https://github.com/stnolting/neo430/tree/master/sw/example)
|
* The NEO430 project also includes some example programs from which you can start your own application: [SW example projects](https://github.com/stnolting/neo430/tree/master/sw/example)
|
|
|
* Have fun! =)
|
* Have fun! =)
|
|
|
|
|
|
|
## Change Log
|
## Change Log
|
|
|
The official change log of this project can be found at the end of the [ NEO430 Datasheet](https://raw.githubusercontent.com/stnolting/neo430/master/doc/NEO430.pdf "NEO430 Datasheet from GitHub").
|
The official change log of this project can be found at the end of the [ NEO430 Datasheet](https://raw.githubusercontent.com/stnolting/neo430/master/doc/NEO430.pdf "NEO430 Datasheet from GitHub").
|
|
|
|
|
|
|
## Contact
|
## Contact
|
|
|
If you have any questions, bug reports, ideas or if you are facing problems with the NEO430 or want to give some kinf of feedback, open a
|
If you have any questions, bug reports, ideas or if you are facing problems with the NEO430 or want to give some kinf of feedback, open a
|
[new issue](https://github.com/stnolting/neo430/issues) or directly drop me a line:
|
[new issue](https://github.com/stnolting/neo430/issues) or directly drop me a line:
|
|
|
stnolting@gmail.com
|
stnolting@gmail.com
|
|
|
|
|
|
|
## Citation
|
## Citation
|
|
|
If you are using the NEO430 Processor in some kind of publication, please cite it as follows:
|
If you are using the NEO430 Processor in some kind of publication, please cite it as follows:
|
|
|
> S. Nolting, "The NEO430 Processor", github.com/stnolting/neo430
|
> S. Nolting, "The NEO430 Processor", github.com/stnolting/neo430
|
|
|
|
|
|
|
## Disclaimer, Proprietary and Legal Notice
|
## Disclaimer, Proprietary and Legal Notice
|
|
|
This is a hobby project released under the BSD 3-Clause license. No copyright infringement intended.
|
This is a hobby project released under the BSD 3-Clause license. No copyright infringement intended.
|
|
|
**BSD 3-Clause License**
|
**BSD 3-Clause License**
|
|
|
Copyright (c) 2020, Stephan Nolting. All rights reserved.
|
Copyright (c) 2020, Stephan Nolting. All rights reserved.
|
|
|
Redistribution and use in source and binary forms, with or without modification, are
|
Redistribution and use in source and binary forms, with or without modification, are
|
permitted provided that the following conditions are met:
|
permitted provided that the following conditions are met:
|
|
|
1. Redistributions of source code must retain the above copyright notice, this list of
|
1. Redistributions of source code must retain the above copyright notice, this list of
|
conditions and the following disclaimer.
|
conditions and the following disclaimer.
|
2. Redistributions in binary form must reproduce the above copyright notice, this list of
|
2. Redistributions in binary form must reproduce the above copyright notice, this list of
|
conditions and the following disclaimer in the documentation and/or other materials
|
conditions and the following disclaimer in the documentation and/or other materials
|
provided with the distribution.
|
provided with the distribution.
|
3. Neither the name of the copyright holder nor the names of its contributors may be used to
|
3. Neither the name of the copyright holder nor the names of its contributors may be used to
|
endorse or promote products derived from this software without specific prior written
|
endorse or promote products derived from this software without specific prior written
|
permission.
|
permission.
|
|
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS
|
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
|
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
|
OF THE POSSIBILITY OF SUCH DAMAGE.
|
OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
|
"MSP430" and "Code Composer Studio" are trademarks of Texas Instruments Corporation.
|
"MSP430" and "Code Composer Studio" are trademarks of Texas Instruments Corporation.
|
|
|
"Windows" is a trademark of Microsoft Corporation.
|
"Windows" is a trademark of Microsoft Corporation.
|
|
|
"Virtex", "Artix" and "Vivado" are trademarks of Xilinx Inc.
|
"Virtex", "Artix" and "Vivado" are trademarks of Xilinx Inc.
|
|
|
"Cyclone", "Quartus" and "Avalon Bus" are trademarks of Intel Corporation.
|
"Cyclone", "Quartus" and "Avalon Bus" are trademarks of Intel Corporation.
|
|
|
"iCE40 UltraPlus", "Lattice Radiant" and "Lattice Diamond" are trademarks of Lattice Semiconductor Corporation.
|
"iCE40 UltraPlus", "Lattice Radiant" and "Lattice Diamond" are trademarks of Lattice Semiconductor Corporation.
|
|
|
"AXI", "AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc.
|
"AXI", "AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc.
|
|
|
|
|
[](https://travis-ci.com/stnolting/neo430)
|
[](https://travis-ci.com/stnolting/neo430)
|
|
|
Continous integration provided by [Travis CI](https://travis-ci.com/stnolting/neo430).
|
Continous integration provided by [Travis CI](https://travis-ci.com/stnolting/neo430).
|
|
|
|
|
|
|
|
|
This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
|
This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
|
|
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|
|
Made with :beer: in Hannover, Germany.
|
Made with :beer: in Hannover, Germany.
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|
