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## Introduction
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## Introduction
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The **NEORV32 processor** is a customizable full-scale mikrocontroller-like processor system based on the RISC-V-compliant
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The **NEORV32 processor** is a customizable full-scale mikrocontroller-like processor system based on the RISC-V-compliant
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`rv32i` NEORV32 CPU with optional `M`, `E`, `C` and `Zicsr` and `Zifencei` extensions. The CPU was built from scratch and
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`rv32i` NEORV32 CPU with optional `M`, `E`, `C` and `U`, `Zicsr` and `Zifencei` extensions and optional physical memory protection (PMP).
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is compliant to the *Unprivileged ISA Specification Version 2.2* and a subset of the *Privileged Architecture
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The CPU was built from scratch and is compliant to the *Unprivileged ISA Specification Version 2.2* and a subset of the *Privileged Architecture
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Specification Version 1.12-draft*.
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Specification Version 1.12-draft*.
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The **processor** is intended as auxiliary processor within a larger SoC designs or as stand-alone
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The **processor** is intended as auxiliary processor within a larger SoC designs or as stand-alone
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custom microcontroller. Its top entity can be directly synthesized for any FPGA without modifications and
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custom microcontroller. Its top entity can be directly synthesized for any FPGA without modifications and
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provides a full-scale RISC-V based microcontroller with common peripherals like GPIO, serial interfaces for
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provides a full-scale RISC-V based microcontroller with common peripherals like GPIO, serial interfaces for
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[compile the GCC toolchains](https://github.com/riscv/riscv-gnu-toolchain) by yourself, you can also
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[compile the GCC toolchains](https://github.com/riscv/riscv-gnu-toolchain) by yourself, you can also
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download [pre-compiled toolchains](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux.
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download [pre-compiled toolchains](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux.
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For more information take a look a the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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For more information take a look a the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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### Key Features
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- RISC-V-compliant `rv32i` CPU with optional `C`, `E`, `M`, `U`, `Zicsr`, `rv32Zifencei` and PMP (physical memory protection) extensions
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- GCC-based toolchain ([pre-compiled rv32i and rv32 etoolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
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- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)
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- Detailed [datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)
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- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc.
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- Fully synchronous design, no latches, no gated clocks
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- Small hardware footprint and high operating frequency
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- Highly configurable CPU and processor setup
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### Design Principles
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### Design Principles
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* From zero to main(): Completely open source and documented.
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* From zero to main(): Completely open source and documented.
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* Plain VHDL without technology-specific parts like attributes, macros or primitives.
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* Plain VHDL without technology-specific parts like attributes, macros or primitives.
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* No exception is triggered for the `E` CPU extension when using registers above `x15` (*needs fixing*)
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* No exception is triggered for the `E` CPU extension when using registers above `x15` (*needs fixing*)
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* `misa` CSR is read-only - no dynamic enabling/disabling of implemented CPU extensions during runtime
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* `misa` CSR is read-only - no dynamic enabling/disabling of implemented CPU extensions during runtime
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* `mcause` CSR is read-only
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* `mcause` CSR is read-only
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* The `[m]cycleh` and `[m]instreth` CSR counters are only 20-bit wide (in contrast to original 32-bit)
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* The `[m]cycleh` and `[m]instreth` CSR counters are only 20-bit wide (in contrast to original 32-bit)
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* The physical memory protection (**PMP**) only supports `NAPOT` mode and only up to 8 regions
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### Custom CPU Extensions
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### Custom CPU Extensions
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The custom extensions are always enabled and are indicated via the `X` bit in the `misa` CSR.
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* Four *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause`
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* Four *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause`
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### To-Do / Wish List
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### To-Do / Wish List
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- Add instructions how to use the NEORV32 CPU without the processor surroundings
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- Add AXI / AXI-Lite bridges
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- Add AXI / AXI-Lite bridges
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- Option to use DSP-based multiplier in `M` extension (would be so much faster)
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- Option to use DSP-based multiplier in `M` extension (would be so much faster)
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- Synthesis results for more platforms
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- Synthesis results for more platforms
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- Implement user mode (`U` extension)
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- Port Dhrystone benchmark
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- Port Dhrystone benchmark
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- Implement atomic operations (`A` extension) and floating-point operations (`F` extension)
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- Implement atomic operations (`A` extension) and floating-point operations (`F` extension)
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- Maybe port an RTOS (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr), [freeRTOS](https://www.freertos.org) or [RIOT](https://www.riot-os.org))
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- Maybe port an RTOS (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr), [freeRTOS](https://www.freertos.org) or [RIOT](https://www.riot-os.org))
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- Make a 64-bit branch someday
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- Make a 64-bit branch someday
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### Processor Features
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### Processor Features
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- RISC-V-compliant `rv32i` CPU with optional `C`, `E`, `M`, `Zicsr` and `rv32Zifencei` extensions
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Highly customizable processor configuration:
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- GCC-based toolchain ([pre-compiled rv32i and rv32 etoolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
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- Optional processor-internal data and instruction memories (DMEM/IMEM)
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- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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- Optional internal bootloader with UART console and automatic SPI flash boot option
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- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)
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- Optional machine system timer (MTIME), RISC-V-compliant
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- Detailed [datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)
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- Optional universal asynchronous receiver and transmitter (UART)
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- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc.
|
- Optional 8/16/24/32-bit serial peripheral interface controller (SPI) with 8 dedicated chip select lines
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- Fully synchronous design, no latches, no gated clocks
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- Optional two wire serial interface controller (TWI), compatible to the I²C standard
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- Small hardware footprint and high operating frequency
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- Optional general purpose parallel IO port (GPIO), 16xOut & 16xIn, with pin-change interrupt
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- Highly customizable processor configuration
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- Optional 32-bit external bus interface, Wishbone b4 compliant (WISHBONE)
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- _Optional_ processor-internal data and instruction memories (DMEM/IMEM)
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- Optional watchdog timer (WDT)
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- _Optional_ internal bootloader with UART console and automatic SPI flash boot option
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- Optional PWM controller with 4 channels and 8-bit duty cycle resolution (PWM)
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- _Optional_ machine system timer (MTIME), RISC-V-compliant
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- Optional GARO-based true random number generator (TRNG)
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- _Optional_ universal asynchronous receiver and transmitter (UART)
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- Optional dummy device (DEVNULL) (can be used for *fast* simulation console output)
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- _Optional_ 8/16/24/32-bit serial peripheral interface controller (SPI) with 8 dedicated chip select lines
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- _Optional_ two wire serial interface controller (TWI), compatible to the I²C standard
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- _Optional_ general purpose parallel IO port (GPIO), 16xOut & 16xIn, with pin-change interrupt
|
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- _Optional_ 32-bit external bus interface, Wishbone b4 compliant (WISHBONE)
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- _Optional_ watchdog timer (WDT)
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- _Optional_ PWM controller with 4 channels and 8-bit duty cycle resolution (PWM)
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- _Optional_ GARO-based true random number generator (TRNG)
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- _Optional_ dummy device (DEVNULL) (can be used for *fast* simulation console output)
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- System configuration information memory to check hardware configuration by software (SYSINFO)
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- System configuration information memory to check hardware configuration by software (SYSINFO)
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### CPU Features
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### CPU Features
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**General**:
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**General**:
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* Modified Harvard architecture (separate CPU interfaces for data and instructions; single processor-bus via bus switch)
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* Modified Harvard architecture (separate CPU interfaces for data and instructions; single processor-bus via bus switch)
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* Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle processing scheme
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* Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle processing scheme
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* No hardware support of unaligned accesses - they will trigger and exception
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* No hardware support of unaligned accesses - they will trigger an exception
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* Privilege levels: `machine` mode, `user` mode (if enabled via `U` extension)
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**RV32I base instruction set** (`I` extension):
|
**RV32I base instruction set** (`I` extension):
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* ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND`
|
* ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND`
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* Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
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* Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
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* Load address misaligned
|
* Load address misaligned
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* Load access fault
|
* Load access fault
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* Store address misaligned
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* Store address misaligned
|
* Store access fault
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* Store access fault
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* Environment call from M-mode (via `ecall` instruction)
|
* Environment call from M-mode (via `ecall` instruction)
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* Machine timer interrupt `mti` (via MTIME unit)
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* Machine timer interrupt `mti` (via processor's MTIME unit)
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* Machine external interrupt `mei` (via CLIC unit)
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* Machine software interrupt `msi` (via external signal)
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|
* Machine external interrupt `mei` (via external signal)
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|
* Four fast interrupt requests (custom extension)
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|
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**Privileged architecture / User mode** (`U` extension, requires `Zicsr` extension):
|
|
* Privilege levels: `M-mode` (Machine mode) + `U-Mode` (User mode)
|
|
|
**Privileged architecture / FENCE.I** (`Zifencei` extension):
|
**Privileged architecture / FENCE.I** (`Zifencei` extension):
|
* System instructions: `FENCE.I`
|
* System instructions: `FENCEI`
|
|
|
|
**Physical memory protection** (`PMP`, requires `Zicsr` extension):
|
|
* Additional machine CSRs: `pmpcfgx` `pmpaddrx`
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|
|
|
|
## FPGA Implementation Results
|
## FPGA Implementation Results
|
|
|
This chapter shows exemplary implementation results of the NEORV32 processor for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
|
This chapter shows exemplary implementation results of the NEORV32 processor for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
|
a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing
|
a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing
|
information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
|
information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
|
of the processor's generics is assumed. No constraints were used at all.
|
of the CPU's generics is assumed (no PMP). No constraints were used at all.
|
|
|
### CPU
|
### CPU
|
|
|
Results generated for hardware version: `1.3.0.0`
|
Results generated for hardware version: `1.3.0.0`
|
|
|
| Line 227... |
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|
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|
|
### Exemplary FPGA Setups
|
### Exemplary FPGA Setups
|
|
|
Exemplary implementation results for different FPGA platforms. The processor setup uses *all provided peripherals*,
|
Exemplary implementation results for different FPGA platforms. The processor setup uses *all provided peripherals*,
|
no external memory interface and only internal instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup's top entity connects most of the
|
no external memory interface, no PMP and only internal instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup's top entity connects most of the
|
processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals
|
processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals
|
to FPGA pins - except for the Wishbone bus and the interrupt signals.
|
to FPGA pins - except for the Wishbone bus and the interrupt signals.
|
|
|
Results generated for hardware version: `1.3.0.0`
|
Results generated for hardware version: `1.3.0.0`
|
|
|
| Line 323... |
Line 336... |
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
|
-- Physical Memory Protection (PMP) --
|
|
PMP_USE : boolean := false; -- implement PMP?
|
|
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 16)
|
|
PMP_GRANULARITY : natural := 15; -- region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
|
-- Memory configuration: Instruction memory --
|
-- Memory configuration: Instruction memory --
|
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
|
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
|
MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
|
MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
|
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
|
| Line 404... |
Line 422... |
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
|
-- Physical Memory Protection (PMP) --
|
|
PMP_USE : boolean := false; -- implement PMP?
|
|
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 16)
|
|
PMP_GRANULARITY : natural := 15; -- region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
|
-- Bus Interface --
|
-- Bus Interface --
|
BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
|
BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
| Line 467... |
Line 490... |
`mul`/`div` instructions! Hence, this code cannot be executed (without emulation) on an architecture without these extensions!
|
`mul`/`div` instructions! Hence, this code cannot be executed (without emulation) on an architecture without these extensions!
|
|
|
To build the toolchain by yourself, follow the official [build instructions](https://github.com/riscv/riscv-gnu-toolchain.
|
To build the toolchain by yourself, follow the official [build instructions](https://github.com/riscv/riscv-gnu-toolchain.
|
Make sure to use the `ilp32` or `ilp32e` ABI.
|
Make sure to use the `ilp32` or `ilp32e` ABI.
|
|
|
Alternatively, you can download a prebuilt toolchain. I have uploaded the toolchain(s) I am using to GitHub. This toolchain
|
**Alternatively**, you can download a prebuilt toolchain. I have uploaded the toolchains I am using to GitHub. These toolchains
|
has been compiled on a 64-bit x86 Ubuntu (Ubuntu on Windows, actually). Download the toolchain of choice:
|
were compiled on a 64-bit x86 Ubuntu 20.04 LTS (Ubuntu on Windows, actually). Download the toolchain of choice:
|
|
|
[https://github.com/stnolting/riscv_gcc_prebuilt](https://github.com/stnolting/riscv_gcc_prebuilt)
|
[https://github.com/stnolting/riscv_gcc_prebuilt](https://github.com/stnolting/riscv_gcc_prebuilt)
|
|
|
|
|
### Dowload the NEORV32 and Create a Hardware Project
|
### Dowload the NEORV32 and Create a Hardware Project
|
