Subversion Repositories neorv32

* Four *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause`

* Four *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause`

### To-Do / Wish List

### To-Do / Wish List

- Option to use DSP-based multiplier in `M` extension (would be so much faster)

- Option to use DSP-based multiplier in `M` extension (would be so much faster)

- Synthesis results for more platforms

- Synthesis results for more platforms

- Port Dhrystone benchmark

- Port Dhrystone benchmark

- Implement atomic operations (`A` extension) and floating-point operations (`F` extension)

- Implement atomic operations (`A` extension) and floating-point operations (`F` extension)

- Maybe port an RTOS (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr), [freeRTOS](https://www.freertos.org) or [RIOT](https://www.riot-os.org))

- Maybe port an RTOS (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr), [freeRTOS](https://www.freertos.org) or [RIOT](https://www.riot-os.org))

    * Machine software interrupt `msi` (via external signal)

    * Machine software interrupt `msi` (via external signal)

    * Machine external interrupt `mei` (via external signal)

    * Machine external interrupt `mei` (via external signal)

    * Four fast interrupt requests (custom extension)

    * Four fast interrupt requests (custom extension)

**Privileged architecture / User mode** (`U` extension, requires `Zicsr` extension):

**Privileged architecture / User mode** (`U` extension, requires `Zicsr` extension):

**Privileged architecture / FENCE.I** (`Zifencei` extension):

**Privileged architecture / FENCE.I** (`Zifencei` extension):

  * System instructions: `FENCEI`

  * System instructions: `FENCEI`

**Physical memory protection** (`PMP`, requires `Zicsr` extension):

**Physical memory protection** (`PMP`, requires `Zicsr` extension):

The top entity of the **processor** is [**neorv32_top.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) (from the `rtl/core` folder).

The top entity of the **processor** is [**neorv32_top.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) (from the `rtl/core` folder).

Just instantiate this file in your project and you are ready to go! All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively

Just instantiate this file in your project and you are ready to go! All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively

(except for the TWI signals, which are of type *std_logic*).

(except for the TWI signals, which are of type *std_logic*).

The top entity of the **CPU** is [**neorv32_cpu.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd) (from the `rtl/core` folder).

The top entity of the **CPU** is [**neorv32_cpu.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd) (from the `rtl/core` folder).

Use the generics to configure the processor/CPU according to your needs. Each generic is initilized with the default configuration.

Use the generics to configure the processor/CPU according to your needs. Each generic is initilized with the default configuration.

Detailed information regarding the signals and configuration generics can be found in the [NEORV32 documentary](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).

Detailed information regarding the signals and configuration generics can be found in the [NEORV32 documentary](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).

Alternative top entities can be found in [`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder.

Alternative top entities can be found in [`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder.

    CPU_EXTENSION_RISCV_U        : boolean := false;  -- implement user mode extension?

    CPU_EXTENSION_RISCV_U        : boolean := false;  -- implement user mode extension?

    CPU_EXTENSION_RISCV_Zicsr    : boolean := true;   -- implement CSR system?

    CPU_EXTENSION_RISCV_Zicsr    : boolean := true;   -- implement CSR system?

    CPU_EXTENSION_RISCV_Zifencei : boolean := true;   -- implement instruction stream sync.?

    CPU_EXTENSION_RISCV_Zifencei : boolean := true;   -- implement instruction stream sync.?

    -- Physical Memory Protection (PMP) --

    -- Physical Memory Protection (PMP) --

    PMP_USE                      : boolean := false;  -- implement PMP?

    PMP_USE                      : boolean := false;  -- implement PMP?

    -- Memory configuration: Instruction memory --

    -- Memory configuration: Instruction memory --

    MEM_ISPACE_BASE              : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space

    MEM_ISPACE_BASE              : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space

    MEM_ISPACE_SIZE              : natural := 16*1024; -- total size of instruction memory space in byte

    MEM_ISPACE_SIZE              : natural := 16*1024; -- total size of instruction memory space in byte

    MEM_INT_IMEM_USE             : boolean := true;   -- implement processor-internal instruction memory

    MEM_INT_IMEM_USE             : boolean := true;   -- implement processor-internal instruction memory

    MEM_INT_IMEM_SIZE            : natural := 16*1024; -- size of processor-internal instruction memory in bytes

    MEM_INT_IMEM_SIZE            : natural := 16*1024; -- size of processor-internal instruction memory in bytes

    CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?

    CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?

    CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?

    CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?

    CPU_EXTENSION_RISCV_Zifencei : boolean := true;  -- implement instruction stream sync.?

    CPU_EXTENSION_RISCV_Zifencei : boolean := true;  -- implement instruction stream sync.?

    -- Physical Memory Protection (PMP) --

    -- Physical Memory Protection (PMP) --

    PMP_USE                      : boolean := false; -- implement PMP?

    PMP_USE                      : boolean := false; -- implement PMP?

    -- Bus Interface --

    -- Bus Interface --

    BUS_TIMEOUT                  : natural := 15     -- cycles after which a valid bus access will timeout

    BUS_TIMEOUT                  : natural := 15     -- cycles after which a valid bus access will timeout

  );

  );

  port (

  port (

    -- global control --

    -- global control --