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# [The NEORV32 Processor](https://github.com/stnolting/neorv32) (RISC-V-compliant)
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# [The NEORV32 Processor](https://github.com/stnolting/neorv32) (RISC-V)
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[](https://travis-ci.com/stnolting/neorv32)
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[](https://travis-ci.com/stnolting/neorv32)
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[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[](https://github.com/stnolting/neorv32/releases)
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[](https://github.com/stnolting/neorv32/releases)
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[compile the GCC toolchains](https://github.com/riscv/riscv-gnu-toolchain) by yourself, you can also
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[compile the GCC toolchains](https://github.com/riscv/riscv-gnu-toolchain) by yourself, you can also
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download [pre-compiled toolchains](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux.
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download [pre-compiled toolchains](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux.
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For more information take a look a the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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For more information take a look a the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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This project is hosted on [GitHub](https://github.com/stnolting/neorv32) and [opencores.org](https://opencores.org/projects/neorv32).
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A not-so-complete project log can be found on [hackaday.io](https://hackaday.io/project/174167-the-neorv32-risc-v-processor).
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### Key Features
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### Key Features
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- RISC-V-compliant `rv32i` CPU with optional `C`, `E`, `M`, `U`, `Zicsr`, `Zifencei` and PMP (physical memory protection) extensions
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- RISC-V-compliant `rv32i` CPU with optional `C`, `E`, `M`, `U`, `Zicsr`, `Zifencei` and PMP (physical memory protection) extensions
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- GCC-based toolchain ([pre-compiled rv32i and rv32e toolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
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- GCC-based toolchain ([pre-compiled rv32i and rv32e toolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
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- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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- Add AXI(-Lite) bridges
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- Add AXI(-Lite) bridges
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- Synthesis results for more platforms
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- Synthesis results for more platforms
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- Port Dhrystone benchmark
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- Port Dhrystone benchmark
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- Implement atomic operations (`A` extension) and floating-point operations (`F` extension)
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- Implement atomic operations (`A` extension) and floating-point operations (`F` extension)
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- Maybe port an RTOS (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr), [freeRTOS](https://www.freertos.org) or [RIOT](https://www.riot-os.org))
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- Maybe port an RTOS (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr), [freeRTOS](https://www.freertos.org) or [RIOT](https://www.riot-os.org))
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- Make a 64-bit branch someday
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## Features
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## Features
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| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 19.1 | balanced | `rv32imcu` + `Zicsr` + `Zifencei` | 3800 (17%) | 1706 (8%) | 0 (0%) | 231424 (38%) | - | - | 100 MHz |
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| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 19.1 | balanced | `rv32imcu` + `Zicsr` + `Zifencei` | 3800 (17%) | 1706 (8%) | 0 (0%) | 231424 (38%) | - | - | 100 MHz |
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| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (LSE) | timing | `rv32icu` + `Zicsr` + `Zifencei` | 4950 (93%) | 1641 (31%) | 0 (0%) | - | 12 (40%) | 4 (100%) | *c* 22.875 MHz |
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| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (LSE) | timing | `rv32icu` + `Zicsr` + `Zifencei` | 4950 (93%) | 1641 (31%) | 0 (0%) | - | 12 (40%) | 4 (100%) | *c* 22.875 MHz |
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| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | default | `rv32imcu` + `Zicsr` + `Zifencei` | 2445 (12%) | 1893 (4%) | 0 (0%) | - | 8 (16%) | - | *c* 100 MHz |
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| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | default | `rv32imcu` + `Zicsr` + `Zifencei` | 2445 (12%) | 1893 (4%) | 0 (0%) | - | 8 (16%) | - | *c* 100 MHz |
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**Notes**
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**Notes**
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* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DEMEM (each 64kb).
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* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DMEM (each 64kb).
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The FPGA-specific memory components can be found in [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up).
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The FPGA-specific memory components can be found in [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up).
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* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are _f_max_ results from the place and route timing reports.
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* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are _f_max_ results from the place and route timing reports.
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* The Upduino and the Arty board have on-board SPI flash memories for storing the FPGA configuration. These device can also be used by the default NEORV32
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* The Upduino and the Arty board have on-board SPI flash memories for storing the FPGA configuration. These device can also be used by the default NEORV32
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bootloader to store and automatically boot an application program after reset (both tested successfully).
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bootloader to store and automatically boot an application program after reset (both tested successfully).
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The [CoreMark CPU benchmark](https://www.eembc.org/coremark) was executed on the NEORV32 and is available in the
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The [CoreMark CPU benchmark](https://www.eembc.org/coremark) was executed on the NEORV32 and is available in the
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[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark
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[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark
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tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.
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tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.
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Results generated for hardware version: `1.3.6.5`
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Results generated for hardware version: `1.3.7.0`
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~~~
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~~~
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**Configuration**
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**Configuration**
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Hardware: 32kB IMEM, 16kB DMEM, 100MHz clock
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Hardware: 32kB IMEM, 16kB DMEM, 100MHz clock
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CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
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CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
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Peripherals: UART for printing the results
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Peripherals: UART for printing the results
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~~~
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~~~
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| CPU | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz |
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| CPU | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz |
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|:---------------------|:---------------:|:------------:|:--------------:|:-------------:|
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|:---------------------|:---------------:|:------------:|:--------------:|:-------------:|
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| `rv32i` | 26 764 bytes | `-O3` | 28.98 | 0.2898 |
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| `rv32i` | 26 748 bytes | `-O3` | 28.98 | 0.2898 |
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| `rv32im` | 25 612 bytes | `-O3` | 58.82 | 0.5882 |
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| `rv32im` | 25 580 bytes | `-O3` | 60.60 | 0.6060 |
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| `rv32imc` | 19 652 bytes | `-O3` | 60.61 | 0.6061 |
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| `rv32imc` | 19 636 bytes | `-O3` | 62.50 | 0.6250 |
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| `rv32imc` + FAST_MUL | 19 652 bytes | `-O3` | 71.43 | 0.7143 |
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| `rv32imc` + FAST_MUL | 19 636 bytes | `-O3` | 74.07 | 0.7407 |
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The _FAST_MUL_ configuration uses DSPs for the multiplier of the `M` extensions (enabled via the `FAST_MUL_EN` generic).
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The _FAST_MUL_ configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic).
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### Instruction Cycles
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### Instruction Cycles
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The NEORV32 CPU is based on a two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme. Hence,
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The NEORV32 CPU is based on a two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme. Hence,
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each instruction requires several clock cycles to execute (2 cycles for ALU operations, ..., 40 cycles for divisions).
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each instruction requires several clock cycles to execute (2 cycles for ALU operations, ..., 40 cycles for divisions).
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The following table shows the performance results for successfully running 2000 CoreMark
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The following table shows the performance results for successfully running 2000 CoreMark
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iterations, which reflects a pretty good "real-life" work load. The average CPI is computed by
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iterations, which reflects a pretty good "real-life" work load. The average CPI is computed by
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dividing the total number of required clock cycles (only the timed core to avoid distortion due to IO wait cycles; sampled via the `cycle[h]` CSRs)
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dividing the total number of required clock cycles (only the timed core to avoid distortion due to IO wait cycles; sampled via the `cycle[h]` CSRs)
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by the number of executed instructions (`instret[h]` CSRs). The executables were generated using optimization `-O3`.
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by the number of executed instructions (`instret[h]` CSRs). The executables were generated using optimization `-O3`.
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Results generated for hardware version: `1.3.6.5`
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Results generated for hardware version: `1.3.7.0`
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| CPU | Required Clock Cycles | Executed Instructions | Average CPI |
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| CPU | Required Clock Cycles | Executed Instructions | Average CPI |
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|:---------------------|----------------------:|----------------------:|:-----------:|
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|:---------------------|----------------------:|----------------------:|:-----------:|
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| `rv32i` | 6 984 305 325 | 1 468 927 290 | 4.75 |
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| `rv32i` | 6 955 817 507 | 1 468 927 290 | 4.73 |
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| `rv32im` | 3 415 761 325 | 601 565 734 | 5.67 |
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| `rv32im` | 3 376 961 507 | 601 565 750 | 5.61 |
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| `rv32imc` | 3 398 881 094 | 601 565 832 | 5.65 |
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| `rv32imc` | 3 274 832 513 | 601 565 964 | 5.44 |
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| `rv32imc` + FAST_MUL | 2 835 121 094 | 601 565 846 | 4.71 |
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| `rv32imc` + FAST_MUL | 2 711 072 513 | 601 566 024 | 4.51 |
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The _FAST_MUL_ configuration uses DSPs for the multiplier of the `M` extensions (enabled via the `FAST_MUL_EN` generic).
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The _FAST_MUL_ configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic).
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## Top Entities
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## Top Entities
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The top entity of the **processor** is [**neorv32_top.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) (from the `rtl/core` folder).
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The top entity of the **processor** is [**neorv32_top.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) (from the `rtl/core` folder).
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