Subversion Repositories neorv32

### Processor Features

### Processor Features

![neorv32 Overview](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_processor.png)

![neorv32 Overview](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_processor.png)

The NEORV32 Processor provides a full-scale microcontroller-like SoC based on the NEORV32 CPU. The setup

The NEORV32 Processor provides a full-scale microcontroller-like SoC based on the NEORV32 CPU. The setup

- Optional processor-internal data and instruction memories (**DMEM** / **IMEM**)

- Optional processor-internal data and instruction memories (**DMEM** / **IMEM**)

- Optional internal **Bootloader** with UART console and automatic SPI flash boot option

- Optional internal **Bootloader** with UART console and automatic SPI flash boot option

- Optional machine system timer (**MTIME**), RISC-V-compliant

- Optional machine system timer (**MTIME**), RISC-V-compliant

- Optional universal asynchronous receiver and transmitter (**UART**)

- Optional universal asynchronous receiver and transmitter (**UART**)

More information regarding the CPU including a detailed list of the instruction set and the available CSRs can be found in

More information regarding the CPU including a detailed list of the instruction set and the available CSRs can be found in

the [![NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/PDF_32.png) NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).

the [![NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/PDF_32.png) NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).

**General**:

**General**:

  * Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle processing scheme

  * Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle processing scheme

  * No hardware support of unaligned accesses - they will trigger an exception

  * No hardware support of unaligned accesses - they will trigger an exception

  * Little-endian byte order

  * Little-endian byte order

  * All reserved or unimplemented instructions will raise an illegal instruction exception

  * All reserved or unimplemented instructions will raise an illegal instruction exception

  * Privilege levels: `machine` mode, `user` mode (if enabled via `U` extension)

  * Privilege levels: `machine` mode, `user` mode (if enabled via `U` extension)

### NEORV32 CPU

### NEORV32 CPU

This chapter shows exemplary implementation results of the NEORV32 CPU for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on

This chapter shows exemplary implementation results of the NEORV32 CPU for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on

a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing

a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing

information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration

information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration

| CPU Configuration                | LEs        | FFs      | Memory bits | DSPs | f_max   |

| CPU Configuration                | LEs        | FFs      | Memory bits | DSPs | f_max   |

### NEORV32 Processor-Internal Peripherals and Memories

### NEORV32 Processor-Internal Peripherals and Memories

| Module    | Description                                          | LEs | FFs | Memory bits | DSPs |

| Module    | Description                                          | LEs | FFs | Memory bits | DSPs |

|:----------|:-----------------------------------------------------|:---:|:---:|:-----------:|:----:|

|:----------|:-----------------------------------------------------|:---:|:---:|:-----------:|:----:|

| CFU       | Custom functions unit                                |   - |   - |           - |    - |

| CFU       | Custom functions unit                                |   - |   - |           - |    - |

| PWM       | Pulse-width modulation controller                    |  72 |  69 |           0 |    0 |

| PWM       | Pulse-width modulation controller                    |  72 |  69 |           0 |    0 |

| SYSINFO   | System configuration information memory              |  10 |   9 |           0 |    0 |

| SYSINFO   | System configuration information memory              |  10 |   9 |           0 |    0 |

### NEORV32 Processor - Exemplary FPGA Setups

### NEORV32 Processor - Exemplary FPGA Setups

Exemplary processor implementation results for different FPGA platforms. The processor setup uses *all provided peripherals* (but not the _CFU_),

Exemplary processor implementation results for different FPGA platforms. The processor setup uses *all provided peripherals* (but not the _CFU_),

no external memory interface and only internal instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup's top entity connects most of the

no external memory interface and only internal instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup's top entity connects most of the

processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals

processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals

to FPGA pins - except for the Wishbone bus and the interrupt signals.

to FPGA pins - except for the Wishbone bus and the interrupt signals.

| Vendor  | FPGA                              | Board            | Toolchain                  | Strategy | CPU Configuration                         | LUT / LE   | FF / REG   | DSP    | Memory Bits  | BRAM / EBR | SPRAM    | Frequency      |

| Vendor  | FPGA                              | Board            | Toolchain                  | Strategy | CPU Configuration                         | LUT / LE   | FF / REG   | DSP    | Memory Bits  | BRAM / EBR | SPRAM    | Frequency      |

**_Notes_**

**_Notes_**

* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DMEM (each 64kb).

* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DMEM (each 64kb).

The FPGA-specific memory components can be found in [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up).

The FPGA-specific memory components can be found in [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up).

* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are _f_max_ results from the place and route timing reports.

* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are _f_max_ results from the place and route timing reports.

Alternative top entities, like the simplified ["hello world" test setup](#Create-a-new-Hardware-Project), can be found

Alternative top entities, like the simplified ["hello world" test setup](#Create-a-new-Hardware-Project), can be found

in [`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder.

in [`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder.

```vhdl

```vhdl

entity neorv32_cpu is

entity neorv32_cpu is

  generic (

  generic (

    -- General --

    -- General --

  );

  );

end neorv32_cpu;

end neorv32_cpu;

```

```

```vhdl

```vhdl

entity neorv32_top is

entity neorv32_top is

  generic (

  generic (

    -- General --

    -- General --

This project is released under the BSD 3-Clause license. No copyright infringement intended.

This project is released under the BSD 3-Clause license. No copyright infringement intended.

Other implied or used projects might have different licensing - see their documentation to get more information.

Other implied or used projects might have different licensing - see their documentation to get more information.

#### Citation

#### Citation

#### BSD 3-Clause License

#### BSD 3-Clause License

Copyright (c) 2020, Stephan Nolting. All rights reserved.

Copyright (c) 2020, Stephan Nolting. All rights reserved.