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* [Introduction](#Introduction)
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* [Introduction](#Introduction)
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* [Features](#Features)
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* [Features](#Features)
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* [FPGA Implementation Results](#FPGA-Implementation-Results)
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* [FPGA Implementation Results](#FPGA-Implementation-Results)
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* [Performance](#Performance)
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* [Performance](#Performance)
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* [Top Entity](#Top-Entity)
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* [Top Entities](#Top-Entities)
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* [**Getting Started**](#Getting-Started)
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* [**Getting Started**](#Getting-Started)
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* [Contribute](#Contribute)
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* [Contribute](#Contribute)
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* [Legal](#Legal)
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* [Legal](#Legal)
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makefiles, a runtime environment, several example programs to start with - including a free RTOS demo - and
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makefiles, a runtime environment, several example programs to start with - including a free RTOS demo - and
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even a builtin bootloader for easy program upload via UART.
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even a builtin bootloader for easy program upload via UART.
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All software source files provide a doxygen-based documentary (available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)).
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All software source files provide a doxygen-based documentary (available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)).
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### [How to get started?](Getting-Started)
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### [How to get started?](#Getting-Started)
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The processor is intended to work "out of the box". Just synthesize the
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The processor is intended to work "out of the box". Just synthesize the
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[test setup](#Create-a-new-Hardware-Project), upload it to your FPGA board of choice and start playing
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[test setup](#Create-a-new-Hardware-Project), upload it to your FPGA board of choice and start playing
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with the NEORV32. If you do not want to [compile the GCC toolchains](https://github.com/riscv/riscv-gnu-toolchain) by yourself, you can also
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with the NEORV32. If you do not want to [compile the GCC toolchains](https://github.com/riscv/riscv-gnu-toolchain) by yourself, you can also
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download [pre-compiled toolchains](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux.
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download [pre-compiled toolchains](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux.
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* The processor has to fit in a Lattice iCE40 UltraPlus 5k FPGA running at 20+ MHz.
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* The processor has to fit in a Lattice iCE40 UltraPlus 5k FPGA running at 20+ MHz.
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### Status
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### Status
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The processor is synthesizable (tested with Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/Synplify Pro) and can successfully execute
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The processor is [synthesizable](#NEORV32-Processor-Exemplary-FPGA-Setups) (tested with *real hardware* using Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/Synplify Pro) and can successfully execute
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all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the CoreMark benchmark.
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all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the [CoreMark benchmark](#CoreMark-Benchmark).
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The processor passes the official `rv32i`, `rv32im`, `rv32imc`, `rv32Zicsr` and `rv32Zifencei` [RISC-V compliance tests](https://github.com/riscv/riscv-compliance).
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The processor passes the official `rv32i`, `rv32im`, `rv32imc`, `rv32Zicsr` and `rv32Zifencei` [RISC-V compliance tests](https://github.com/riscv/riscv-compliance).
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| Project component | CI status | Note |
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| Project component | CI status | Note |
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|:--------------------------------------------------------------------------------|:----------|:---------|
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|:--------------------------------------------------------------------------------|:----------|:---------|
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is highly customizable via the processor's top generics.
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is highly customizable via the processor's top generics.
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- Optional processor-internal data and instruction memories (**DMEM** / **IMEM**)
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- Optional processor-internal data and instruction memories (**DMEM** / **IMEM**)
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- Optional internal **Bootloader** with UART console and automatic SPI flash boot option
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- Optional internal **Bootloader** with UART console and automatic SPI flash boot option
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- Optional machine system timer (**MTIME**), RISC-V-compliant
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- Optional machine system timer (**MTIME**), RISC-V-compliant
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- Optional universal asynchronous receiver and transmitter (**UART**)
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- Optional universal asynchronous receiver and transmitter (**UART**) with simulation output option via text.io
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- Optional 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines
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- Optional 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines
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- Optional two wire serial interface controller (**TWI**), compatible to the I²C standard
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- Optional two wire serial interface controller (**TWI**), compatible to the I²C standard
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- Optional general purpose parallel IO port (**GPIO**), 32xOut & 32xIn, with pin-change interrupt
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- Optional general purpose parallel IO port (**GPIO**), 32xOut & 32xIn, with pin-change interrupt
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- Optional 32-bit external bus interface, Wishbone b4 compliant (**WISHBONE**)
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- Optional 32-bit external bus interface, Wishbone b4 compliant (**WISHBONE**)
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- Optional watchdog timer (**WDT**)
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- Optional watchdog timer (**WDT**)
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- Optional PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**)
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- Optional PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**)
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- Optional GARO-based true random number generator (**TRNG**)
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- Optional GARO-based true random number generator (**TRNG**)
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- Optional dummy device (**DEVNULL**); used for debugging; can also be used for *fast* simulation console output
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- Optional custom functions unit (**CFU**) for tightly-coupled custom co-processors
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- Optional custom functions unit (**CFU**) for tightly-coupled custom co-processors
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- System configuration information memory to check hardware configuration by software (**SYSINFO**)
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- System configuration information memory to check hardware configuration by software (**SYSINFO**)
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### CPU Features
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### CPU Features
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**Privileged architecture / CSR access** (`Zicsr` extension):
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**Privileged architecture / CSR access** (`Zicsr` extension):
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* Privilege levels: `M-mode` (Machine mode)
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* Privilege levels: `M-mode` (Machine mode)
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* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
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* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
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* System instructions: `MRET` `WFI`
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* System instructions: `MRET` `WFI`
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* Counter CSRs: `cycle` `cycleh` `instret` `instreth` `time` `timeh` `mcycle` `mcycleh` `minstret` `minstreth`
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* Counter CSRs: `cycle` `cycleh` `instret` `instreth` `time` `timeh` `mcycle` `mcycleh` `minstret` `minstreth`
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* Machine CSRs: `mstatus` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause`(read-only!) `mtval` `mip` `mvendorid` [`marchid`](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md) `mimpid` `mhartid` `mzext`(custom)
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* Machine CSRs: `mstatus` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mvendorid` [`marchid`](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md) `mimpid` `mhartid` `mzext`(custom)
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* Supported exceptions and interrupts:
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* Supported exceptions and interrupts:
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* Misaligned instruction address
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* Misaligned instruction address
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* Instruction access fault
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* Instruction access fault
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* Illegal instruction
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* Illegal instruction
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* Breakpoint (via `ebreak` instruction)
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* Breakpoint (via `ebreak` instruction)
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| Line 214... |
Line 213... |
* Additional machine CSRs: `pmpcfg0` `pmpcfg1` `pmpaddr0` `pmpaddr1` `pmpaddr2` `pmpaddr3` `pmpaddr4` `pmpaddr5` `pmpaddr6` `pmpaddr7`
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* Additional machine CSRs: `pmpcfg0` `pmpcfg1` `pmpaddr0` `pmpaddr1` `pmpaddr2` `pmpaddr3` `pmpaddr4` `pmpaddr5` `pmpaddr6` `pmpaddr7`
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### Non-RISC-V-Compliant Issues
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### Non-RISC-V-Compliant Issues
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|
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* `misa` CSR is read-only - no dynamic enabling/disabling of synthesized CPU extensions during runtime
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* `misa` CSR is read-only - no dynamic enabling/disabling of synthesized CPU extensions during runtime; for compatibility: write accesses (in m-mode) are ignored and do not cause an exception
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* `mcause` CSR is read-only
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* The physical memory protection (**PMP**) only supports `NAPOT` mode, a minimal granularity of 8 bytes and only up to 8 regions
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* The physical memory protection (**PMP**) only supports `NAPOT` mode, a minimal granularity of 8 bytes and only up to 8 regions
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### NEORV32-Specific CPU Extensions
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### NEORV32-Specific CPU Extensions
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Line 255... |
| Module | Description | LEs | FFs | Memory bits | DSPs |
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| Module | Description | LEs | FFs | Memory bits | DSPs |
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|:----------|:-----------------------------------------------------|:---:|:---:|:-----------:|:----:|
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|:----------|:-----------------------------------------------------|:---:|:---:|:-----------:|:----:|
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| BOOT ROM | Bootloader ROM (default 4kB) | 3 | 1 | 32 768 | 0 |
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| BOOT ROM | Bootloader ROM (default 4kB) | 3 | 1 | 32 768 | 0 |
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| BUSSWITCH | Mux for CPU I & D interfaces | 59 | 8 | 0 | 0 |
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| BUSSWITCH | Mux for CPU I & D interfaces | 59 | 8 | 0 | 0 |
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| CFU | Custom functions unit | - | - | - | - |
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| CFU | Custom functions unit | - | - | - | - |
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| DEVNULL | Dummy device | 1 | 1 | 0 | 0 |
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| DMEM | Processor-internal data memory (default 8kB) | 13 | 2 | 65 536 | 0 |
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| DMEM | Processor-internal data memory (default 8kB) | 13 | 2 | 65 536 | 0 |
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| GPIO | General purpose input/output ports | 69 | 65 | 0 | 0 |
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| GPIO | General purpose input/output ports | 69 | 65 | 0 | 0 |
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| IMEM | Processor-internal instruction memory (default 16kb) | 9 | 2 | 131 072 | 0 |
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| IMEM | Processor-internal instruction memory (default 16kb) | 9 | 2 | 131 072 | 0 |
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| MTIME | Machine system timer | 281 | 166 | 0 | 0 |
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| MTIME | Machine system timer | 281 | 166 | 0 | 0 |
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| PWM | Pulse-width modulation controller | 72 | 69 | 0 | 0 |
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| PWM | Pulse-width modulation controller | 72 | 69 | 0 | 0 |
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## Top Entities
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## Top Entities
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|
|
The top entity of the **NEORV32 Processor** is [**neorv32_top.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) (from the `rtl/core` folder).
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The top entity of the **NEORV32 Processor** is [**neorv32_top.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) (from `rtl/core`).
|
Just instantiate this file in your project and you are ready to go! All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively
|
Just instantiate this file in your project and you are ready to go! All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively
|
(except for the TWI signals, which are of type *std_logic*).
|
(except for the TWI signals, which are of type *std_logic*).
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|
|
The top entity of the **NEORV32 CPU** is [**neorv32_cpu.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd) (from the `rtl/core` folder).
|
The top entity of the **NEORV32 CPU** is [**neorv32_cpu.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd) (from `rtl/core`).
|
All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively.
|
All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively.
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|
|
Use the generics to configure the processor/CPU according to your needs. Each generic is initilized with the default configuration.
|
Use the generics to configure the processor/CPU according to your needs. Each generic is initilized with the default configuration.
|
Detailed information regarding the signals and configuration generics can be found in
|
Detailed information regarding the signals and configuration generics can be found in
|
the [NEORV32 documentary](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
the [NEORV32 documentary](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
|
|
Alternative top entities, like the simplified ["hello world" test setup](#Create-a-new-Hardware-Project), can be found
|
Alternative top entities, like the simplified ["hello world" test setup](#Create-a-new-Hardware-Project) or CPU/Processor
|
in [`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder.
|
wrappers with resolved port signal types (i.e. *std_logic*), can be found in [`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates).
|
|
|
|
|
### NEORV32 CPU
|
### NEORV32 CPU
|
|
|
```vhdl
|
```vhdl
|
| Line 389... |
Line 386... |
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
-- Physical Memory Protection (PMP) --
|
-- Physical Memory Protection (PMP) --
|
PMP_USE : boolean := false; -- implement PMP?
|
PMP_USE : boolean := false; -- implement PMP?
|
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
|
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
|
PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
|
PMP_GRANULARITY : natural := 14 -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
|
-- Bus Interface --
|
|
BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
|
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
| Line 464... |
Line 459... |
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
|
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
|
-- External memory interface --
|
-- External memory interface --
|
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2)
|
MEM_EXT_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2)
|
MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout
|
|
-- Processor peripherals --
|
-- Processor peripherals --
|
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
|
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
|
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
|
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
|
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
|
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
|
IO_DEVNULL_USE : boolean := true; -- implement dummy device (DEVNULL)?
|
|
IO_CFU_USE : boolean := false -- implement custom functions unit (CFU)?
|
IO_CFU_USE : boolean := false -- implement custom functions unit (CFU)?
|
);
|
);
|
port (
|
port (
|
-- Global control --
|
-- Global control --
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
