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[](https://github.com/stnolting/neorv32/releases)
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[](https://github.com/stnolting/neorv32/releases)
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## Table of Content
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## Table of Content
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* [Introduction](#Introduction)
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* [Overview](#Overview)
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* [Project Status](#Status)
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* [Features](#Features)
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* [Features](#Features)
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* [FPGA Implementation Results](#FPGA-Implementation-Results)
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* [FPGA Implementation Results](#FPGA-Implementation-Results)
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* [Performance](#Performance)
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* [Performance](#Performance)
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* [Top Entities](#Top-Entities)
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* [Top Entities](#Top-Entities)
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* [**Getting Started**](#Getting-Started)
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* [**Getting Started**](#Getting-Started)
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* [Contribute](#Contribute)
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* [Contribute](#Contribute)
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* [Legal](#Legal)
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* [Legal](#Legal)
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## Introduction
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## Overview
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based
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on the RISC-V-compliant NEORV32 CPU. The project consists of two main parts:
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on the RISC-V-compliant NEORV32 CPU. The project consists of two main parts:
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stand-alone mode and build your own SoC around it.
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stand-alone mode and build your own SoC around it.
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### [NEORV32 Processor](#Processor-Features)
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### [NEORV32 Processor](#Processor-Features)
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Based on the NEORV32 CPU, the NEORV32 Processor is a full-scale RISC-V microcontroller system
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Based on the NEORV32 CPU, the NEORV32 Processor is a full-scale RISC-V microcontroller system (**SoC**)
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that already provides common peripherals like GPIO, serial interfaces, timers, embedded
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that already provides common peripherals like GPIO, serial interfaces, timers, embedded
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memories and an external bus interface for connectivity and custom extension.
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memories and an external bus interface for connectivity and custom extension.
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All optional features and modules beyond the base CPU can be enabled and configured via
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All optional features and modules beyond the base CPU can be enabled and configured via
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[VHDL generics](#Top-Entities).
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[VHDL generics](#Top-Entities).
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For more information take a look at the [ NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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For more information take a look at the [ NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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### Key Features
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### Key Features
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- RISC-V-compliant `rv32i` CPU with optional `C`, `E`, `M`, `U`, `Zicsr`, `Zifencei` and `PMP` (physical memory protection) extensions
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* RISC-V-compliant `rv32i` CPU with optional `C`, `E`, `M`, `U`, `Zicsr`, `Zifencei` and `PMP` (physical memory protection) extensions
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- GCC-based toolchain ([pre-compiled rv32i and rv32e toolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
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* GCC-based toolchain ([pre-compiled rv32i and rv32e toolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
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- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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* Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)
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* [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)
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- [**Detailed data sheet**](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)
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* [**Detailed data sheet**](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)
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- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc.
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* Completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
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- Fully synchronous design, no latches, no gated clocks
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* Fully synchronous design, no latches, no gated clocks
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- Small hardware footprint and high operating frequency
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* Small hardware footprint and high operating frequency
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- Highly configurable CPU and processor setup
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* Highly configurable CPU and processor setup
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- [FreeRTOS port](https://github.com/stnolting/neorv32/blob/master/sw/example/demo_freeRTOS) available
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* [FreeRTOS port](https://github.com/stnolting/neorv32/blob/master/sw/example/demo_freeRTOS) available
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### Design Principles
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### Design Principles
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* From zero to main(): Completely open source and documented.
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* From zero to `main()`: Completely open source and documented.
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* Plain VHDL without technology-specific parts like attributes, macros or primitives.
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* Plain VHDL without technology-specific parts like attributes, macros or primitives.
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* Easy to use – working out of the box.
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* Easy to use – working out of the box.
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* Clean synchronous design, no wacky combinatorial interfaces.
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* Clean synchronous design, no wacky combinatorial interfaces.
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* Be as small as possible – but with a reasonable size-performance tradeoff.
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* Be as small as possible – but with a reasonable size-performance tradeoff.
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* The processor has to fit in a Lattice iCE40 UltraPlus 5k FPGA running at 20+ MHz.
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* The processor has to fit in a Lattice iCE40 UltraPlus 5k FPGA running at 20+ MHz.
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### Status
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## Status
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The processor is [synthesizable](#FPGA-Implementation-Results) (tested on *real hardware* using Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/Synplify Pro) and can successfully execute
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The processor is [synthesizable](#FPGA-Implementation-Results) (tested on *real hardware* using Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/Synplify Pro) and can successfully execute
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all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the [CoreMark benchmark](#CoreMark-Benchmark).
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all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the [CoreMark benchmark](#CoreMark-Benchmark).
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The processor passes the official `rv32i`, `rv32im`, `rv32imc`, `rv32Zicsr` and `rv32Zifencei` [RISC-V compliance tests](https://github.com/riscv/riscv-compliance).
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The processor passes the official `rv32i`, `rv32im`, `rv32imc`, `rv32Zicsr` and `rv32Zifencei` [RISC-V compliance tests](https://github.com/riscv/riscv-compliance).
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| [RISC-V compliance test](https://github.com/stnolting/neorv32_riscv_compliance) | [](https://travis-ci.com/stnolting/neorv32_riscv_compliance) | |
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| [RISC-V compliance test](https://github.com/stnolting/neorv32_riscv_compliance) | [](https://travis-ci.com/stnolting/neorv32_riscv_compliance) | |
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### To-Do / Wish List
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### To-Do / Wish List
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- Add AXI(-Lite) bridges
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* Add AXI(-Lite) bridges
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- Synthesis results (+ wrappers?) for more platforms
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* Synthesis results (+ wrappers?) for more platforms
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- Maybe port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))
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* Maybe port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))
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- Implement further CPU extensions:
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* Implement further CPU extensions:
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- Atomic operations (`A`)
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* Atomic operations (`A`)
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- Bitmanipulation operations (`B`), when they are "official"
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* Bitmanipulation operations (`B`), when they are "official"
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- Floating-point instructions (`F`)
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* Floating-point instructions (`F`)
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- ...
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* ...
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## Features
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## Features
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The full-blown data sheet of the NEORV32 Processor/CPU is available as pdf file:
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The full-blown data sheet of the NEORV32 Processor/CPU is available as pdf file:
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The NEORV32 Processor provides a full-scale microcontroller-like SoC based on the NEORV32 CPU. The setup
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The NEORV32 Processor provides a full-scale microcontroller-like SoC based on the NEORV32 CPU. The setup
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is highly customizable via the processor's top generics.
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is highly customizable via the processor's top generics.
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- Optional processor-internal data and instruction memories (**DMEM** / **IMEM**)
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* Optional processor-internal data and instruction memories (**DMEM** / **IMEM**)
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- Optional internal **Bootloader** with UART console and automatic SPI flash boot option
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* Optional internal **Bootloader** with UART console and automatic SPI flash boot option
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- Optional machine system timer (**MTIME**), RISC-V-compliant
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* Optional machine system timer (**MTIME**), RISC-V-compliant
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- Optional universal asynchronous receiver and transmitter (**UART**) with simulation output option via text.io
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* Optional universal asynchronous receiver and transmitter (**UART**) with simulation output option via text.io
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- Optional 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines
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* Optional 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines
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- Optional two wire serial interface controller (**TWI**), compatible to the I²C standard
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* Optional two wire serial interface controller (**TWI**), compatible to the I²C standard
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- Optional general purpose parallel IO port (**GPIO**), 32xOut & 32xIn, with pin-change interrupt
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* Optional general purpose parallel IO port (**GPIO**), 32xOut & 32xIn, with pin-change interrupt
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- Optional 32-bit external bus interface, Wishbone b4 compliant (**WISHBONE**), *standard* or *pipelined* handshake/transactions mode
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* Optional 32-bit external bus interface, Wishbone b4 compliant (**WISHBONE**), *standard* or *pipelined* handshake/transactions mode
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- Optional watchdog timer (**WDT**)
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* Optional watchdog timer (**WDT**)
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- Optional PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**)
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* Optional PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**)
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- Optional GARO-based true random number generator (**TRNG**)
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* Optional GARO-based true random number generator (**TRNG**)
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- Optional custom functions unit (**CFU**) for tightly-coupled custom co-processors
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* Optional custom functions unit (**CFU**) for tightly-coupled custom co-processors
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- System configuration information memory to check hardware configuration by software (**SYSINFO**)
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* System configuration information memory to check hardware configuration by software (**SYSINFO**)
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### CPU Features
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### CPU Features
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~~~
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~~~
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**Configuration**
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**Configuration**
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Hardware: 32kB IMEM, 16kB DMEM, 100MHz clock
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Hardware: 32kB IMEM, 16kB DMEM, 100MHz clock
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CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
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CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
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Compiler: RISCV32-GCC 10.1.0 (rv32i)
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Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain)
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Flags: default, see makefile
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Peripherals: UART for printing the results
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Peripherals: UART for printing the results
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~~~
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~~~
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| CPU | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz |
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| CPU | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz |
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|:--------------------------|:---------------:|:------------:|:--------------:|:-------------:|
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|:--------------------------|:---------------:|:------------:|:--------------:|:-------------:|
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| `rv32i` | 26 940 bytes | `-O3` | 33.89 | 0.3389 |
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| `rv32i` | 26 940 bytes | `-O3` | 33.89 | **0.3389** |
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| `rv32im` | 25 772 bytes | `-O3` | 64.51 | 0.6451 |
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| `rv32im` | 25 772 bytes | `-O3` | 64.51 | **0.6451** |
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| `rv32im` + `FAST_MUL_EN` | 25 772 bytes | `-O3` | 80.00 | 0.8000 |
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| `rv32imc` | 20 524 bytes | `-O3` | 64.51 | **0.6451** |
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| `rv32imc` | 19 812 bytes | `-O3` | 62.50 | 0.6250 |
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| `rv32imc` + `FAST_MUL_EN` | 20 524 bytes | `-O3` | 80.00 | **0.8000** |
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| `rv32imc` + `FAST_MUL_EN` | 19 812 bytes | `-O3` | 76.92 | 0.7692 |
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The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic).
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The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic).
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When the `C` extension is enabled, branches to an unaligned uncompressed instruction require additional instruction fetch cycles.
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When the `C` extension is enabled, branches to an unaligned uncompressed instruction require additional instruction fetch cycles.
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Results generated for hardware version: `1.4.4.8`
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Results generated for hardware version: `1.4.4.8`
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| CPU | Required Clock Cycles | Executed Instructions | Average CPI |
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| CPU | Required Clock Cycles | Executed Instructions | Average CPI |
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|:------------------------|----------------------:|----------------------:|:-----------:|
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|:------------------------|----------------------:|----------------------:|:-----------:|
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| `rv32i` | 5 945 938 586 | 1 469 587 406 | 4.05 |
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| `rv32i` | 5 945 938 586 | 1 469 587 406 | **4.05** |
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| `rv32im` | 3 110 282 586 | 602 225 760 | 5.16 |
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| `rv32im` | 3 110 282 586 | 602 225 760 | **5.16** |
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| `rv32im` `FAST_MUL_EN` | 2 527 730 586 | 602 225 728 | 4.19 |
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| `rv32imc` | 3 172 969 968 | 615 388 924 | **5.16** |
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| `rv32imc` | 3 217 064 278 | 602 225 530 | 5.34 |
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| `rv32imc` `FAST_MUL_EN` | 2 590 417 968 | 615 388 890 | **4.21** |
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| `rv32imc` `FAST_MUL_EN` | 2 634 512 278 | 602 225 574 | 4.37 |
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The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic).
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The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic).
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When the `C` extension is enabled, branches to an unaligned uncompressed instruction require additional instruction fetch cycles.
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When the `C` extension is enabled, branches to an unaligned uncompressed instruction require additional instruction fetch cycles.
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### Upload the Executable via the Bootloader
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### Upload the Executable via the Bootloader
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|
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Connect your FPGA board via UART to your computer and open the according port to interface with the NEORV32 bootloader. The bootloader
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Connect your FPGA board via UART to your computer and open the according port to interface with the NEORV32 bootloader. The bootloader
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uses the following default UART configuration:
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uses the following default UART configuration:
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- 19200 Baud
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* 19200 Baud
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- 8 data bits
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* 8 data bits
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- 1 stop bit
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* 1 stop bit
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- No parity bits
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* No parity bits
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- No transmission / flow control protocol (raw bytes only)
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* No transmission / flow control protocol (raw bytes only)
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- Newline on `\r\n` (carriage return & newline) - also for sent data
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* Newline on `\r\n` (carriage return & newline) - also for sent data
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Use the bootloader console to upload the `neorv32_exe.bin` executable and run your application image.
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Use the bootloader console to upload the `neorv32_exe.bin` executable and run your application image.
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```
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```
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<< NEORV32 Bootloader >>
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<< NEORV32 Bootloader >>
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This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
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This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
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--------
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This repository was created on June 23th, 2020.
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Made with :coffee: in Hannover, Germany.
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Made with :coffee: in Hannover, Germany.
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