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# [The NEORV32 Processor](https://github.com/stnolting/neorv32) (RISC-V)
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[](https://github.com/stnolting/neorv32)
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# The NEORV32 RISC-V Processor
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[](https://travis-ci.com/stnolting/neorv32)
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[](https://travis-ci.com/stnolting/neorv32)
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[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[](https://github.com/stnolting/neorv32/releases)
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[](https://github.com/stnolting/neorv32/releases)
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## Overview
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## Overview
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based
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on the RISC-V-compliant NEORV32 CPU. The processor is intended as *ready-to-go* auxiliary processor within a larger SoC
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on the RISC-V-compliant NEORV32 CPU. The processor is intended as *ready-to-go* auxiliary processor within a larger SoC
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designs or as stand-alone custom microcontroller. Its top entity can be directly synthesized for *any* target technology without modifications.
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designs or as stand-alone custom microcontroller.
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### Key Features
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### Key Features
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* RISC-V-[compliant](#Status) 32-bit `rv32i` [**NEORV32 CPU**](#NEORV32-CPU-Features)
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* RISC-V-[compliant](#Status) 32-bit `rv32i` [**NEORV32 CPU**](#NEORV32-CPU-Features), compliant to
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* Compliant to *Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf)
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* Subset of the *Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf)
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* Compliant to *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf)
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* Subset of the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf)
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* Optional CPU extensions
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* Optional CPU extensions
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* `C` - compressed instructions (16-bit)
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* `C` - compressed instructions (16-bit)
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* `E` - embedded CPU (reduced register file)
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* `E` - embedded CPU (reduced register file)
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* `M` - integer multiplication and division hardware
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* `M` - integer multiplication and division hardware
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* `U` - less-privileged *user mode*
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* `U` - less-privileged *user mode*
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* `Zicsr` - control and status register access instructions (+ exception/irq system)
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* `Zicsr` - control and status register access instructions (+ exception/irq system)
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* `Zifencei` - instruction stream synchronization
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* `Zifencei` - instruction stream synchronization
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* `PMP` - physical memory protection
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* `PMP` - physical memory protection
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* Full-scale RISC-V microcontroller system (**SoC**) [**NEORV32 Processor**](#NEORV32-Processor-Features) with optional submodules
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* optional embedded memories (instruction/data/bootloader, RAM/ROM)
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* timers (watch dog, RISC-V-compliant machine timer)
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* serial interfaces (SPI, TWI, UART)
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* external bus interface (Wishbone / [AXI4](#AXI4-Connectivity))
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* [more ...](#NEORV32-Processor-Features)
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* Software framework
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* Software framework
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* Core libraries for high-level usage of the provided functions and peripherals
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* core libraries for high-level usage of the provided functions and peripherals
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* Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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* application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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* GCC-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
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* GCC-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
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* runtime environment
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* runtime environment
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* several example programs
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* several example programs
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* [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)
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* [doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)
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* [FreeRTOS port](https://github.com/stnolting/neorv32/blob/master/sw/example/demo_freeRTOS) available
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* [FreeRTOS port](https://github.com/stnolting/neorv32/blob/master/sw/example/demo_freeRTOS) available
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* [**Full-blown data sheet**](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)
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* [**Full-blown data sheet**](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)
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* Completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
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* Completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
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* Fully synchronous design, no latches, no gated clocks
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* Fully synchronous design, no latches, no gated clocks
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* Small hardware footprint and high operating frequency
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* Small hardware footprint and high operating frequency
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* Full-scale RISC-V microcontroller system (**SoC**): [**NEORV32 Processor**](#NEORV32-Processor-Features)
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* Optional embedded memories, timers, serial interfaces, external interfaces (Wishbone or [AXI4-Lite](#AXI4-Connectivity)) ...
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The project’s change log is available in the [CHANGELOG.md](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) file in the root directory of this repository.
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The project’s change log is available in the [CHANGELOG.md](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) file in the root directory of this repository.
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To see the changes between releases visit the project's [release page](https://github.com/stnolting/neorv32/releases).
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To see the changes between releases visit the project's [release page](https://github.com/stnolting/neorv32/releases).
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For more information take a look at the [NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf).
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For more information take a look at the [NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf).
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### To-Do / Wish List / [Help Wanted](#Contribute)
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### To-Do / Wish List / [Help Wanted](#Contribute)
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* Use LaTeX for data sheet
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* Use LaTeX for data sheet
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* More support for FreeRTOS
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* Further size and performance optimization
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* Further size and performance optimization
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* Add a cache for the external memory interface
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* Add a cache for the external memory interface
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* Synthesis results (+ wrappers?) for more/specific platforms
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* Synthesis results (+ wrappers?) for more/specific platforms
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* Maybe port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))
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* Maybe port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))
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* Implement further CPU extensions:
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* Implement further CPU extensions:
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### NEORV32 Processor Features
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### NEORV32 Processor Features
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The NEORV32 Processor provides a full-scale microcontroller-like SoC based on the NEORV32 CPU. The setup
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The NEORV32 Processor provides a full-scale microcontroller-like SoC based on the NEORV32 CPU. The setup
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is highly customizable via the processor's top generics.
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is highly customizable via the processor's top generics and already provides the following *optional* modules:
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* Optional processor-internal data and instruction memories (**DMEM** / **IMEM**)
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* processor-internal data and instruction memories (**DMEM** / **IMEM**)
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* Optional internal **Bootloader** with UART console and automatic application boot from SPI flash option
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* internal **Bootloader** with UART console and automatic application boot from SPI flash option
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* Optional machine system timer (**MTIME**), RISC-V-compliant
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* machine system timer (**MTIME**), RISC-V-compliant
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* Optional universal asynchronous receiver and transmitter (**UART**) with simulation output option via text.io
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* watchdog timer (**WDT**)
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* Optional 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines
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* universal asynchronous receiver and transmitter (**UART**) with simulation output option via text.io
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* Optional two wire serial interface controller (**TWI**), with optional clock-stretching, compatible to the I²C standard
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* 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines
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* Optional general purpose parallel IO port (**GPIO**), 32xOut & 32xIn, with pin-change interrupt
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* two wire serial interface controller (**TWI**), with optional clock-stretching, compatible to the I²C standard
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* Optional 32-bit external bus interface, Wishbone b4 compliant (**WISHBONE**), *standard* or *pipelined* handshake/transactions mode
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* general purpose parallel IO port (**GPIO**), 32xOut & 32xIn, with pin-change interrupt
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* Optional wrapper for **AXI4-Lite Master Interface** (see [AXI Connectivity](#AXI4-Connectivity)), compatibility verified with Xilinx Vivado Block Desginer
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* 32-bit external bus interface, Wishbone b4 compliant (**WISHBONE**), *standard* or *pipelined* handshake/transactions mode
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* Optional watchdog timer (**WDT**)
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* wrapper for **AXI4-Lite Master Interface** (see [AXI Connectivity](#AXI4-Connectivity))
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* Optional PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**)
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* PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**)
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* Optional GARO-based true random number generator (**TRNG**)
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* GARO-based true random number generator (**TRNG**)
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* Optional custom functions units (**CFU0** and **CFU1**) for tightly-coupled custom co-processors
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* custom functions units (**CFU0** and **CFU1**) for tightly-coupled custom co-processors
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* System configuration information memory to check hardware configuration by software (**SYSINFO**)
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* system configuration information memory to check hardware configuration by software (**SYSINFO**, mandatory - not *optional*)
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### NEORV32 CPU Features
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### NEORV32 CPU Features
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## FPGA Implementation Results
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## FPGA Implementation Results
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### NEORV32 CPU
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### NEORV32 CPU
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This chapter shows exemplary implementation results of the NEORV32 CPU for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
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This chapter shows exemplary implementation results of the NEORV32 CPU for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
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a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing
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a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 20.1** ("balanced implementation"). The timing
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information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
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information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
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of the CPU's generics is assumed (for example no PMP). No constraints were used at all.
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of the CPU's generics is assumed (for example no PMP). No constraints were used at all.
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Results generated for hardware version `1.4.4.8`.
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Results generated for hardware version `1.4.7.0`.
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| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max |
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| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max |
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|:---------------------------------------|:----------:|:--------:|:-----------:|:----:|:--------:|
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|:---------------------------------------|:----------:|:--------:|:-----------:|:----:|:--------:|
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| `rv32i` | 983 | 438 | 2048 | 0 | ~120 MHz |
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| `rv32i` | 932 | 413 | 2048 | 0 | ~120 MHz |
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| `rv32i` + `u` + `Zicsr` + `Zifencei` | 1877 | 802 | 2048 | 0 | ~112 MHz |
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| `rv32i` + `u` + `Zicsr` + `Zifencei` | 1800 | 815 | 2048 | 0 | ~118 MHz |
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| `rv32im` + `u` + `Zicsr` + `Zifencei` | 2374 | 1048 | 2048 | 0 | ~110 MHz |
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| `rv32im` + `u` + `Zicsr` + `Zifencei` | 2368 | 1058 | 2048 | 0 | ~117 MHz |
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| `rv32imc` + `u` + `Zicsr` + `Zifencei` | 2650 | 1064 | 2048 | 0 | ~110 MHz |
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| `rv32imc` + `u` + `Zicsr` + `Zifencei` | 2604 | 1073 | 2048 | 0 | ~113 MHz |
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| `rv32emc` + `u` + `Zicsr` + `Zifencei` | 2680 | 1061 | 1024 | 0 | ~110 MHz |
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| `rv32emc` + `u` + `Zicsr` + `Zifencei` | 2613 | 1073 | 1024 | 0 | ~113 MHz |
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### NEORV32 Processor-Internal Peripherals and Memories
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### NEORV32 Processor-Internal Peripherals and Memories
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Results generated for hardware version `1.4.4.8`.
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Results generated for hardware version `1.4.7.0`.
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| Module | Description | LEs | FFs | Memory bits | DSPs |
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| Module | Description | LEs | FFs | Memory bits | DSPs |
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|:----------|:-----------------------------------------------------|----:|----:|------------:|-----:|
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|:----------|:-----------------------------------------------------|----:|----:|------------:|-----:|
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| BOOT ROM | Bootloader ROM (default 4kB) | 4 | 1 | 32 768 | 0 |
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| BOOT ROM | Bootloader ROM (default 4kB) | 3 | 1 | 32 768 | 0 |
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| BUSSWITCH | Mux for CPU I & D interfaces | 62 | 8 | 0 | 0 |
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| BUSSWITCH | Mux for CPU I & D interfaces | 63 | 8 | 0 | 0 |
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| CFU0 | Custom functions unit 0 | - | - | - | - |
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| CFU0 | Custom functions unit 0 | - | - | - | - |
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| CFU1 | Custom functions unit 1 | - | - | - | - |
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| CFU1 | Custom functions unit 1 | - | - | - | - |
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| DMEM | Processor-internal data memory (default 8kB) | 13 | 2 | 65 536 | 0 |
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| DMEM | Processor-internal data memory (default 8kB) | 12 | 2 | 65 536 | 0 |
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| GPIO | General purpose input/output ports | 66 | 65 | 0 | 0 |
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| GPIO | General purpose input/output ports | 66 | 65 | 0 | 0 |
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| IMEM | Processor-internal instruction memory (default 16kb) | 7 | 2 | 131 072 | 0 |
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| IMEM | Processor-internal instruction memory (default 16kb) | 7 | 2 | 131 072 | 0 |
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| MTIME | Machine system timer | 268 | 166 | 0 | 0 |
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| MTIME | Machine system timer | 272 | 166 | 0 | 0 |
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| PWM | Pulse-width modulation controller | 72 | 69 | 0 | 0 |
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| PWM | Pulse-width modulation controller | 72 | 69 | 0 | 0 |
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| SPI | Serial peripheral interface | 184 | 125 | 0 | 0 |
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| SPI | Serial peripheral interface | 142 | 124 | 0 | 0 |
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| SYSINFO | System configuration information memory | 11 | 9 | 0 | 0 |
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| SYSINFO | System configuration information memory | 11 | 9 | 0 | 0 |
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| TRNG | True random number generator | 132 | 105 | 0 | 0 |
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| TRNG | True random number generator | 132 | 105 | 0 | 0 |
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| TWI | Two-wire interface | 74 | 44 | 0 | 0 |
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| TWI | Two-wire interface | 77 | 44 | 0 | 0 |
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| UART | Universal asynchronous receiver/transmitter | 175 | 132 | 0 | 0 |
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| UART | Universal asynchronous receiver/transmitter | 173 | 132 | 0 | 0 |
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| WDT | Watchdog timer | 58 | 45 | 0 | 0 |
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| WDT | Watchdog timer | 58 | 45 | 0 | 0 |
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| WISHBONE | External memory interface | 106 | 104 | 0 | 0 |
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| WISHBONE | External memory interface | 106 | 104 | 0 | 0 |
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### NEORV32 Processor - Exemplary FPGA Setups
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### NEORV32 Processor - Exemplary FPGA Setups
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Exemplary processor implementation results for different FPGA platforms. The processor setup uses *the default peripheral configuration* (like no _CFUs_ and no _TRNG_),
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Exemplary processor implementation results for different FPGA platforms. The processor setup uses *the default peripheral configuration* (like no _CFUs_ and no _TRNG_),
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no external memory interface and only internal instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup's top entity connects most of the
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no external memory interface and only internal instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup's top entity connects most of the
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processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals
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processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals
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to FPGA pins - except for the Wishbone bus and the interrupt signals.
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to FPGA pins - except for the Wishbone bus and the interrupt signals.
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Results generated for hardware version `1.4.4.8`.
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Results generated for hardware version `1.4.7.0`.
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| Vendor | FPGA | Board | Toolchain | Strategy | CPU Configuration | LUT / LE | FF / REG | DSP | Memory Bits | BRAM / EBR | SPRAM | Frequency |
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| Vendor | FPGA | Board | Toolchain | Strategy | CPU Configuration | LUT / LE | FF / REG | DSP | Memory Bits | BRAM / EBR | SPRAM | Frequency |
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|:--------|:----------------------------------|:-----------------|:---------------------------|:-------- |:-----------------------------------------------|:-----------|:-----------|:-------|:-------------|:-----------|:---------|--------------:|
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|:--------|:----------------------------------|:-----------------|:---------------------------|:-------- |:-----------------------------------------------|:-----------|:-----------|:-------|:-------------|:-----------|:---------|--------------:|
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| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 19.1 | balanced | `rv32imc` + `u` + `Zicsr` + `Zifencei` + `PMP` | 4008 (18%) | 1849 (9%) | 0 (0%) | 231424 (38%) | - | - | 105 MHz |
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| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 20.1 | balanced | `rv32imc` + `u` + `Zicsr` + `Zifencei` + `PMP` | 3892 (17%) | 1859 (8%) | 0 (0%) | 231424 (38%) | - | - | 113 MHz |
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| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (Synplify Pro) | default | `rv32ic` + `u` + `Zicsr` + `Zifencei` | 4296 (81%) | 1611 (30%) | 0 (0%) | - | 12 (40%) | 4 (100%) | *c* 22.5 MHz |
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| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (Synplify Pro) | default | `rv32ic` + `u` + `Zicsr` + `Zifencei` | 4331 (82%) | 1673 (31%) | 0 (0%) | - | 12 (40%) | 4 (100%) | *c* 22.5 MHz |
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| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | default | `rv32imc` + `u` + `Zicsr` + `Zifencei` + `PMP` | 2390 (11%) | 1888 (5%) | 0 (0%) | - | 8 (16%) | - | *c* 100 MHz |
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| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | default | `rv32imc` + `u` + `Zicsr` + `Zifencei` + `PMP` | 2416 (12%) | 1900 (5%) | 0 (0%) | - | 8 (16%) | - | *c* 100 MHz |
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**_Notes_**
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**_Notes_**
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* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DMEM (each 64kb).
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* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DMEM (each 64kb).
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The FPGA-specific memory components can be found in [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up).
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The FPGA-specific memory components can be found in [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up).
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* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are _f_max_ results from the place and route timing reports.
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* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are _f_max_ results from the place and route timing reports.
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The [CoreMark CPU benchmark](https://www.eembc.org/coremark) was executed on the NEORV32 and is available in the
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The [CoreMark CPU benchmark](https://www.eembc.org/coremark) was executed on the NEORV32 and is available in the
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[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark
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[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark
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tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.
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tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.
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Results generated for hardware version `1.4.5.4`.
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Results generated for hardware version `1.4.7.0`.
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~~~
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~~~
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**Configuration**
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**Configuration**
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Hardware: 32kB IMEM, 16kB DMEM, 100MHz clock
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Hardware: 32kB IMEM, 16kB DMEM, 100MHz clock
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CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
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CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
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Peripherals: UART for printing the results
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Peripherals: UART for printing the results
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~~~
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~~~
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| CPU | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz |
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| CPU | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz |
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|:--------------------------------------------|:---------------:|:------------:|:--------------:|:-------------:|
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|:--------------------------------------------|:---------------:|:------------:|:--------------:|:-------------:|
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| `rv32i` | 26 940 bytes | `-O3` | 33.89 | **0.3389** |
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| `rv32i` | 27 424 bytes | `-O3` | 35.71 | **0.3571** |
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| `rv32im` | 25 772 bytes | `-O3` | 64.51 | **0.6451** |
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| `rv32im` | 26 232 bytes | `-O3` | 66.66 | **0.6666** |
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| `rv32imc` | 20 524 bytes | `-O3` | 64.51 | **0.6451** |
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| `rv32imc` | 20 876 bytes | `-O3` | 66.66 | **0.6666** |
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| `rv32imc` + `FAST_MUL_EN` | 20 524 bytes | `-O3` | 80.00 | **0.8000** |
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| `rv32imc` + `FAST_MUL_EN` | 20 876 bytes | `-O3` | 83.33 | **0.8333** |
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| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` | 20 524 bytes | `-O3` | 83.33 | **0.8333** |
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| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` | 20 876 bytes | `-O3` | 86.96 | **0.8696** |
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The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic). The `FAST_SHIFT_EN` configuration
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The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic). The `FAST_SHIFT_EN` configuration
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uses a barrel shifter for CPU shift operations (enabled via the `FAST_SHIFT_EN` generic).
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uses a barrel shifter for CPU shift operations (enabled via the `FAST_SHIFT_EN` generic).
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When the `C` extension is enabled, branches to an unaligned uncompressed instruction require additional instruction fetch cycles.
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When the `C` extension is enabled, branches to an unaligned uncompressed instruction require additional instruction fetch cycles.
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The following table shows the performance results for successfully running 2000 CoreMark
|
The following table shows the performance results for successfully running 2000 CoreMark
|
iterations, which reflects a pretty good "real-life" work load. The average CPI is computed by
|
iterations, which reflects a pretty good "real-life" work load. The average CPI is computed by
|
dividing the total number of required clock cycles (only the timed core to avoid distortion due to IO wait cycles; sampled via the `cycle[h]` CSRs)
|
dividing the total number of required clock cycles (only the timed core to avoid distortion due to IO wait cycles; sampled via the `cycle[h]` CSRs)
|
by the number of executed instructions (`instret[h]` CSRs). The executables were generated using optimization `-O3`.
|
by the number of executed instructions (`instret[h]` CSRs). The executables were generated using optimization `-O3`.
|
|
|
Results generated for hardware version `1.4.5.4`.
|
Results generated for hardware version `1.4.7.0`.
|
|
|
| CPU | Required Clock Cycles | Executed Instructions | Average CPI |
|
| CPU | Required Clock Cycles | Executed Instructions | Average CPI |
|
|:--------------------------------------------|----------------------:|----------------------:|:-----------:|
|
|:--------------------------------------------|----------------------:|----------------------:|:-----------:|
|
| `rv32i` | 5 945 938 586 | 1 469 587 406 | **4.05** |
|
| `rv32i` | 5 648 997 774 | 1 469 233 238 | **3.84** |
|
| `rv32im` | 3 110 282 586 | 602 225 760 | **5.16** |
|
| `rv32im` | 3 036 749 774 | 601 871 338 | **5.05** |
|
| `rv32imc` | 3 172 969 968 | 615 388 890 | **5.16** |
|
| `rv32imc` | 3 036 959 882 | 615 034 616 | **4.94** |
|
| `rv32imc` + `FAST_MUL_EN` | 2 590 417 968 | 615 388 890 | **4.21** |
|
| `rv32imc` + `FAST_MUL_EN` | 2 454 407 882 | 615 034 588 | **3.99** |
|
| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` | 2 456 318 408 | 615 388 890 | **3.99** |
|
| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` | 2 320 308 322 | 615 034 676 | **3.77** |
|
|
|
|
|
The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic). The `FAST_SHIFT_EN` configuration
|
The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic). The `FAST_SHIFT_EN` configuration
|
uses a barrel shifter for CPU shift operations (enabled via the `FAST_SHIFT_EN` generic).
|
uses a barrel shifter for CPU shift operations (enabled via the `FAST_SHIFT_EN` generic).
|
|
|
| Line 498... |
Line 505... |
Use the bootloader console to upload the `neorv32_exe.bin` executable and run your application image.
|
Use the bootloader console to upload the `neorv32_exe.bin` executable and run your application image.
|
|
|
```
|
```
|
<< NEORV32 Bootloader >>
|
<< NEORV32 Bootloader >>
|
|
|
BLDV: Jul 6 2020
|
BLDV: Nov 7 2020
|
HWV: 1.0.1.0
|
HWV: 0x01040606
|
CLK: 0x0134FD90 Hz
|
CLK: 0x0134FD90 Hz
|
USER: 0x0001CE40
|
USER: 0x0001CE40
|
MISA: 0x42801104
|
MISA: 0x42801104
|
PROC: 0x03FF0035
|
PROC: 0x03FF0035
|
IMEM: 0x00010000 bytes @ 0x00000000
|
IMEM: 0x00010000 bytes @ 0x00000000
|
| Line 548... |
Line 555... |
## Legal
|
## Legal
|
|
|
This project is released under the BSD 3-Clause license. No copyright infringement intended.
|
This project is released under the BSD 3-Clause license. No copyright infringement intended.
|
Other implied or used projects might have different licensing - see their documentation to get more information.
|
Other implied or used projects might have different licensing - see their documentation to get more information.
|
|
|
#### Citation
|
#### Citing
|
|
|
If you are using the NEORV32 or some parts of the project in some kind of publication, please cite it as follows:
|
If you are using the NEORV32 or some parts of the project in some kind of publication, please cite it as follows:
|
|
|
> S. Nolting, "The NEORV32 Processor", github.com/stnolting/neorv32
|
> S. Nolting, "The NEORV32 Processor", github.com/stnolting/neorv32
|
|
|
| Line 621... |
Line 628... |
|
|
This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
|
This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
|
|
|
--------
|
--------
|
|
|
This repository was created on June 23th, 2020.
|
This repository was created on June 23rd, 2020.
|
|
|
Made with :coffee: in Hannover, Germany :eu:
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Made with :coffee: in Hannover, Germany :eu:
|
