OpenCores

Rev 42	Rev 43
Line 1...	Line 1...
`[![NEORV32](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_logo.png)](https://github.com/stnolting/neorv32)`	`[![NEORV32](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_logo.png)](https://github.com/stnolting/neorv32)`

`# The NEORV32 RISC-V Processor`	`# The NEORV32 RISC-V Processor`

`[![Build Status](https://travis-ci.com/stnolting/neorv32.svg?branch=master)](https://travis-ci.com/stnolting/neorv32)`	`[![Processor Check](https://github.com/stnolting/neorv32/workflows/Processor%20Check/badge.svg)](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22)`
	`[![RISC-V Compliance](https://github.com/stnolting/neorv32/workflows/RISC-V%20Compliance/badge.svg)](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22RISC-V+Compliance%22)`
`[![license](https://img.shields.io/github/license/stnolting/neorv32)](https://github.com/stnolting/neorv32/blob/master/LICENSE)`	`[![license](https://img.shields.io/github/license/stnolting/neorv32)](https://github.com/stnolting/neorv32/blob/master/LICENSE)`
`[![release](https://img.shields.io/github/v/release/stnolting/neorv32)](https://github.com/stnolting/neorv32/releases)`	`[![release](https://img.shields.io/github/v/release/stnolting/neorv32)](https://github.com/stnolting/neorv32/releases)`

`* [Overview](#Overview)`	`* [Overview](#Overview)`
`* [Project Status](#Status)`	`* [Project Status](#Status)`
Line 80...	Line 81...
`all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the [CoreMark benchmark](#CoreMark-Benchmark).`	`all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the [CoreMark benchmark](#CoreMark-Benchmark).`

The processor passes the official `rv32_m/C`, `rv32_m/I`, `rv32_m/M`, `rv32_m/privilege` and `rv32_m/Zifencei`	The processor passes the official `rv32_m/C`, `rv32_m/I`, `rv32_m/M`, `rv32_m/privilege` and `rv32_m/Zifencei`
`[RISC-V compliance tests (new framework v2)](https://github.com/riscv/riscv-compliance).`	`[RISC-V compliance tests (new framework v2)](https://github.com/riscv/riscv-compliance).`

`\| Project component \| CI status \| Note \|`	`\| Project component \| CI status \|`
`\|:----------------- \|:----------\|:---------\|`	`\|:----------------- \|:----------\|`
`\| [NEORV32 processor](https://github.com/stnolting/neorv32) \| [![Build Status](https://travis-ci.com/stnolting/neorv32.svg?branch=master)](https://travis-ci.com/stnolting/neorv32) \| [![sw doc](https://img.shields.io/badge/SW%20documentation-gh--pages-blue)](https://stnolting.github.io/neorv32/files.html) \|`	`\| [NEORV32 processor](https://github.com/stnolting/neorv32) \| [![Processor Check](https://github.com/stnolting/neorv32/workflows/Processor%20Check/badge.svg)](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22) \|`
`\| [Pre-built toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) \| [![Build Status](https://travis-ci.com/stnolting/riscv_gcc_prebuilt.svg?branch=master)](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) \| \|`	`\| [SW Framework Documentation (online)](https://stnolting.github.io/neorv32/files.html) \| [![Doc@GitHub-pages](https://github.com/stnolting/neorv32/workflows/Deploy%20SW%20Framework%20Documentation%20to%20GitHub-Pages/badge.svg)](https://stnolting.github.io/neorv32/files.html) \|`
`\| RISC-V compliance test \| \| See [riscv-compliance/README.md](https://github.com/stnolting/neorv32/blob/master/riscv-compliance/README.md) \|`	`\| [Pre-built toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) \| [![Test Toolchains](https://github.com/stnolting/riscv_gcc_prebuilt/workflows/Test%20Toolchains/badge.svg)](https://github.com/stnolting/riscv_gcc_prebuilt/actions?query=workflow%3A%22Test+Toolchains%22) \|`
	`\| [RISC-V compliance test](https://github.com/stnolting/neorv32/blob/master/riscv-compliance/README.md) \| [![RISC-V Compliance](https://github.com/stnolting/neorv32/workflows/RISC-V%20Compliance/badge.svg)](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22RISC-V+Compliance%22) \|`



`### To-Do / Wish List / Help Wanted`	`### To-Do / Wish List / Help Wanted`

`* Use LaTeX for data sheet`	`* Use LaTeX for data sheet`
`* Further size and performance optimization [work in progress]`	`* Further size and performance optimization [work in progress]`
`* Add associativity configuration for instruction cache`	`* Add associativity configuration for instruction cache`
`* Add data cache`	`* Add data cache`
`* Burst mode for the external memory/bus interface`	`* Burst mode for the external memory/bus interface`
* RISC-V `F` (using `Zfinx`?) CPU extension (single-precision floating point) [planning]	* RISC-V `F` (using `Zfinx`?) CPU extension (single-precision floating point) [planning]
* RISC-V `B` CPU extension ([bitmanipulation](https://github.com/riscv/riscv-bitmanip)) [shelved]	* RISC-V `B` (using `Zbb`?) CPU extension ([bitmanipulation](https://github.com/riscv/riscv-bitmanip)) [planning]
`* Synthesis results (+ wrappers?) for more/specific platforms`	`* Synthesis results (+ wrappers?) for more/specific platforms`
`* More support for FreeRTOS (like all traps)`	`* More support for FreeRTOS (like all traps)`
`* Port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))`	`* Port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))`
`* Implement further RISC-V (or custom?) CPU extensions`	`* Implement further RISC-V (or custom?) CPU extensions`
`* Add debugger ([RISC-V debug spec](https://github.com/riscv/riscv-debug-spec))`	`* Add debugger ([RISC-V debug spec](https://github.com/riscv/riscv-debug-spec))`
Line 644...	Line 647...

`[![RISC-V](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/riscv_logo.png)](https://riscv.org/)`	`[![RISC-V](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/riscv_logo.png)](https://riscv.org/)`

`[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free!`	`[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free!`

`[![Continous Integration provided by Travis CI](https://travis-ci.com/images/logos/TravisCI-Full-Color.png)](https://travis-ci.com/stnolting/neorv32)`	`Continous integration provided by [:octocat: GitHub Actions](https://github.com/features/actions) and powered by [GHDL](https://github.com/ghdl/ghdl).`

`Continous integration provided by [Travis CI](https://travis-ci.com/stnolting/neorv32) and powered by [GHDL](https://github.com/ghdl/ghdl).`


`![Open Source Hardware Logo https://www.oshwa.org](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/oshw_logo.png)`	`![Open Source Hardware Logo https://www.oshwa.org](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/oshw_logo.png)`

`This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).`	`This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).`

Line 1...

[![NEORV32](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_logo.png)](https://github.com/stnolting/neorv32)

[![NEORV32](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_logo.png)](https://github.com/stnolting/neorv32)

# The NEORV32 RISC-V Processor

# The NEORV32 RISC-V Processor

[![Build Status](https://travis-ci.com/stnolting/neorv32.svg?branch=master)](https://travis-ci.com/stnolting/neorv32)

[![Processor Check](https://github.com/stnolting/neorv32/workflows/Processor%20Check/badge.svg)](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22)

[![RISC-V Compliance](https://github.com/stnolting/neorv32/workflows/RISC-V%20Compliance/badge.svg)](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22RISC-V+Compliance%22)

[![license](https://img.shields.io/github/license/stnolting/neorv32)](https://github.com/stnolting/neorv32/blob/master/LICENSE)

[![license](https://img.shields.io/github/license/stnolting/neorv32)](https://github.com/stnolting/neorv32/blob/master/LICENSE)

[![release](https://img.shields.io/github/v/release/stnolting/neorv32)](https://github.com/stnolting/neorv32/releases)

[![release](https://img.shields.io/github/v/release/stnolting/neorv32)](https://github.com/stnolting/neorv32/releases)

* [Overview](#Overview)

* [Overview](#Overview)

* [Project Status](#Status)

* [Project Status](#Status)

Line 80...

Line 81...

all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the [CoreMark benchmark](#CoreMark-Benchmark).

all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the [CoreMark benchmark](#CoreMark-Benchmark).

The processor passes the official `rv32_m/C`, `rv32_m/I`, `rv32_m/M`, `rv32_m/privilege` and `rv32_m/Zifencei`

The processor passes the official `rv32_m/C`, `rv32_m/I`, `rv32_m/M`, `rv32_m/privilege` and `rv32_m/Zifencei`

[RISC-V compliance tests (new framework v2)](https://github.com/riscv/riscv-compliance).

[RISC-V compliance tests (new framework v2)](https://github.com/riscv/riscv-compliance).

| Project component | CI status | Note     |

| Project component | CI status |

|:----------------- |:----------|:---------|

|:----------------- |:----------|

| [NEORV32 processor](https://github.com/stnolting/neorv32) | [![Build Status](https://travis-ci.com/stnolting/neorv32.svg?branch=master)](https://travis-ci.com/stnolting/neorv32) | [![sw doc](https://img.shields.io/badge/SW%20documentation-gh--pages-blue)](https://stnolting.github.io/neorv32/files.html) |

| [NEORV32 processor](https://github.com/stnolting/neorv32)                                             | [![Processor Check](https://github.com/stnolting/neorv32/workflows/Processor%20Check/badge.svg)](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22) |

| [Pre-built toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) | [![Build Status](https://travis-ci.com/stnolting/riscv_gcc_prebuilt.svg?branch=master)](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) | |

| [SW Framework Documentation (online)](https://stnolting.github.io/neorv32/files.html)                 | [![Doc@GitHub-pages](https://github.com/stnolting/neorv32/workflows/Deploy%20SW%20Framework%20Documentation%20to%20GitHub-Pages/badge.svg)](https://stnolting.github.io/neorv32/files.html) |

| RISC-V compliance test | | See [riscv-compliance/README.md](https://github.com/stnolting/neorv32/blob/master/riscv-compliance/README.md) |

| [Pre-built toolchain](https://github.com/stnolting/riscv_gcc_prebuilt)                                | [![Test Toolchains](https://github.com/stnolting/riscv_gcc_prebuilt/workflows/Test%20Toolchains/badge.svg)](https://github.com/stnolting/riscv_gcc_prebuilt/actions?query=workflow%3A%22Test+Toolchains%22) |

| [RISC-V compliance test](https://github.com/stnolting/neorv32/blob/master/riscv-compliance/README.md) | [![RISC-V Compliance](https://github.com/stnolting/neorv32/workflows/RISC-V%20Compliance/badge.svg)](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22RISC-V+Compliance%22) |

### To-Do / Wish List / Help Wanted

### To-Do / Wish List / Help Wanted

* Use LaTeX for data sheet

* Use LaTeX for data sheet

* Further size and performance optimization *[work in progress]*

* Further size and performance optimization *[work in progress]*

* Add associativity configuration for instruction cache

* Add associativity configuration for instruction cache

* Add *data* cache

* Add *data* cache

* Burst mode for the external memory/bus interface

* Burst mode for the external memory/bus interface

* RISC-V `F` (using `Zfinx`?) CPU extension (single-precision floating point) *[planning]*

* RISC-V `F` (using `Zfinx`?) CPU extension (single-precision floating point) *[planning]*

* RISC-V `B` CPU extension ([bitmanipulation](https://github.com/riscv/riscv-bitmanip)) *[shelved]*

* RISC-V `B` (using `Zbb`?) CPU extension ([bitmanipulation](https://github.com/riscv/riscv-bitmanip)) *[planning]*

* Synthesis results (+ wrappers?) for more/specific platforms

* Synthesis results (+ wrappers?) for more/specific platforms

* More support for FreeRTOS (like *all* traps)

* More support for FreeRTOS (like *all* traps)

* Port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))

* Port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))

* Implement further RISC-V (or custom?) CPU extensions

* Implement further RISC-V (or custom?) CPU extensions

* Add debugger ([RISC-V debug spec](https://github.com/riscv/riscv-debug-spec))

* Add debugger ([RISC-V debug spec](https://github.com/riscv/riscv-debug-spec))

Line 644...

Line 647...

[![RISC-V](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/riscv_logo.png)](https://riscv.org/)

[![RISC-V](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/riscv_logo.png)](https://riscv.org/)

[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free!

[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free!

[![Continous Integration provided by Travis CI](https://travis-ci.com/images/logos/TravisCI-Full-Color.png)](https://travis-ci.com/stnolting/neorv32)

Continous integration provided by [:octocat: GitHub Actions](https://github.com/features/actions) and powered by [GHDL](https://github.com/ghdl/ghdl).

Continous integration provided by [Travis CI](https://travis-ci.com/stnolting/neorv32) and powered by [GHDL](https://github.com/ghdl/ghdl).

![Open Source Hardware Logo https://www.oshwa.org](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/oshw_logo.png)

![Open Source Hardware Logo https://www.oshwa.org](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/oshw_logo.png)

This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).

This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).

Browse

Tools

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [README.md] - Diff between revs 42 and 43