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### Key Features
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### Key Features
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* RISC-V-[compliant](#Status) 32-bit `rv32i` [**NEORV32 CPU**](#NEORV32-CPU-Features), compliant to
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* RISC-V-[compliant](#Status) 32-bit `rv32i` [**NEORV32 CPU**](#NEORV32-CPU-Features), compliant to
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* Subset of the *Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf)
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* Subset of the *Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf)
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* Subset of the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf)
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* Subset of the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf)
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* Optional RISC-V CPU extensions
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* Configurable RISC-V CPU extensions
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* `A` - atomic memory access instructions
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* `A` - atomic memory access instructions (optional)
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* `C` - compressed instructions (16-bit)
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* `B` - Bit manipulation instructions (optional)
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* `E` - embedded CPU (reduced register file)
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* `C` - compressed instructions (16-bit) (optional)
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* `M` - integer multiplication and division hardware
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* `E` - embedded CPU (reduced register file (optional)
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* `U` - less-privileged *user mode*
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* `I` - base integer instruction set (always enabled)
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* `Zicsr` - control and status register access instructions (+ exception/irq system)
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* `M` - integer multiplication and division hardware (optional)
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* `Zifencei` - instruction stream synchronization
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* `U` - less-privileged *user mode* (optional)
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* `PMP` - physical memory protection
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* `X` - NEORV32_specific extensions (always enabled)
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* `Zicsr` - control and status register access instructions (+ exception/irq system) (optional)
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* `Zifencei` - instruction stream synchronization (optional)
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* `PMP` - physical memory protection (optional)
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* `HPM` - hardware performance monitors (optional)
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* Full-scale RISC-V microcontroller system / **SoC** [**NEORV32 Processor**](#NEORV32-Processor-Features) with optional submodules
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* Full-scale RISC-V microcontroller system / **SoC** [**NEORV32 Processor**](#NEORV32-Processor-Features) with optional submodules
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* optional embedded memories (instructions/data/bootloader, RAM/ROM) and caches
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* optional embedded memories (instructions/data/bootloader, RAM/ROM) and caches
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* timers (watch dog, RISC-V-compliant machine timer)
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* timers (watch dog, RISC-V-compliant machine timer)
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* serial interfaces (SPI, TWI, UART) and general purpose IO
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* serial interfaces (SPI, TWI, UART) and general purpose IO
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* external bus interface (Wishbone / [AXI4](#AXI4-Connectivity))
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* external bus interface (Wishbone / [AXI4](#AXI4-Connectivity))
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### To-Do / Wish List / Help Wanted
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### To-Do / Wish List / Help Wanted
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* Use LaTeX for data sheet
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* Use LaTeX for data sheet
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* Further size and performance optimization *[work in progress]*
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* Further size and performance optimization
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* Add associativity configuration for instruction cache
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* Add associativity configuration for instruction cache
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* Add *data* cache
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* Add *data* cache
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* Burst mode for the external memory/bus interface
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* Burst mode for the external memory/bus interface
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* RISC-V `F` (using `Zfinx`?) CPU extension (single-precision floating point) *[planning]*
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* RISC-V `F` (using `[Zfinx](https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc)`?) CPU extension (single-precision floating point)
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* RISC-V `B` (using `Zbb`?) CPU extension ([bitmanipulation](https://github.com/riscv/riscv-bitmanip)) *[planning]*
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* Add template (HW module + intrinsics skeleton) for custom instructions?
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* Synthesis results (+ wrappers?) for more/specific platforms
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* Synthesis results (+ wrappers?) for more/specific platforms
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* More support for FreeRTOS (like *all* traps)
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* More support for FreeRTOS (like *all* traps)
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* Port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))
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* Port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))
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* Implement further RISC-V (or custom?) CPU extensions
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* Implement further RISC-V (or custom?) CPU extensions
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* Add debugger ([RISC-V debug spec](https://github.com/riscv/riscv-debug-spec))
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* Add debugger ([RISC-V debug spec](https://github.com/riscv/riscv-debug-spec))
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## Features
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## Features
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The full-blown data sheet of the NEORV32 Processor and CPU is available as pdf file:
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The full-blown data sheet of the NEORV32 Processor and CPU is available as pdf file:
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[:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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[:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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### NEORV32 Processor Features
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### NEORV32 Processor Features
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The NEORV32 Processor provides a full-scale microcontroller-like SoC based on the NEORV32 CPU. The setup
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The NEORV32 Processor provides a full-scale microcontroller-like SoC based on the NEORV32 CPU. The setup
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* PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**)
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* PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**)
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* GARO-based true random number generator (**TRNG**)
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* GARO-based true random number generator (**TRNG**)
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* custom functions units (**CFU0** and **CFU1**) for tightly-coupled custom co-processors
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* custom functions units (**CFU0** and **CFU1**) for tightly-coupled custom co-processors
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* system configuration information memory to check hardware configuration by software (**SYSINFO**, mandatory - not *optional*)
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* system configuration information memory to check hardware configuration by software (**SYSINFO**, mandatory - not *optional*)
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### NEORV32 CPU Features
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### NEORV32 CPU Features
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The NEORV32 CPU is **compliant** to the
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The NEORV32 CPU is **compliant** to the
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[official RISC-V specifications (2.2)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the
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[official RISC-V specifications (2.2)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the
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[RISC-V privileged architecture specifications (1.12-draft)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf)
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[RISC-V privileged architecture specifications (1.12-draft)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf)
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* Multiplications can be mapped to DSPs via the `FAST_MUL_EN` generic to increase performance
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* Multiplications can be mapped to DSPs via the `FAST_MUL_EN` generic to increase performance
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**Atomic memory access** (`A` extension):
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**Atomic memory access** (`A` extension):
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* Supported instructions: `LR.W` (load-reservate) `SC.W` (store-conditional)
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* Supported instructions: `LR.W` (load-reservate) `SC.W` (store-conditional)
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**Bit manipulation instructions** (`B` extension implying `Zbb` extension):
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* :warning: RISC-V `B` extension is not officially ratified yet!
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* Compatible to [v0.94-draft](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/bitmanip-draft.pdf) of the bit manipulation spec
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* Support via intrisc library (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation))
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* Only the `Zbb` base instructions subset is supported yet
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* Supported instructions: `CLZ` `CTZ` `CPOP` `SEXT.B` `SEXT.H` `MIN[U]` `MAX[U]` `ANDN` `ORN` `XNOR` `ROL` `ROR` `RORI` `zext`(*pseudo-instruction* for `PACK rd, rs, zero`) `rev8`(*pseudo-instruction* for `GREVI rd, rs, -8`) `orc.b`(*pseudo-instruction* for `GORCI rd, rs, 7`)
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**Privileged architecture / CSR access** (`Zicsr` extension):
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**Privileged architecture / CSR access** (`Zicsr` extension):
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* Privilege levels: `M-mode` (Machine mode)
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* Privilege levels: `M-mode` (Machine mode)
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* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
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* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
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* System instructions: `MRET` `WFI`
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* System instructions: `MRET` `WFI`
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* Pseudo-instructions are not listed
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* Pseudo-instructions are not listed
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| Line 211... |
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* Four fast interrupt requests (custom extension)
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* Four fast interrupt requests (custom extension)
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**Privileged architecture / User mode** (`U` extension, requires `Zicsr` extension):
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**Privileged architecture / User mode** (`U` extension, requires `Zicsr` extension):
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* Privilege levels: `M-mode` (Machine mode) + `U-mode` (User mode)
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* Privilege levels: `M-mode` (Machine mode) + `U-mode` (User mode)
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**Privileged architecture / instruction stream synchronization** (`Zifencei` extension):
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**Privileged architecture / Instruction stream synchronization** (`Zifencei` extension):
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* System instructions: `FENCE.I` (among others, used to clear and reload instruction cache)
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* System instructions: `FENCE.I` (among others, used to clear and reload instruction cache)
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**Privileged architecture / Physical memory protection** (`PMP`, requires `Zicsr` extension):
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**Privileged architecture / Physical memory protection** (`PMP`, requires `Zicsr` extension):
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* Configurable number of regions
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* Configurable number of regions (0..63)
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* Additional machine CSRs: `pmpcfg*`(0..15) `pmpaddr*`(0..63)
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* Additional machine CSRs: `pmpcfg*`(0..15) `pmpaddr*`(0..63)
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**Privileged architecture / Hardware performance monitors** (`HPM`, requires `Zicsr` extension):
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* Configurable number of counters (0..29)
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* Additional machine CSRs: `mhpmevent*`(3..31) `[m]hpmcounter*[h]`(3..31)
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### Non-RISC-V-Compliant Issues
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### :warning: Non-RISC-V-Compliant Issues and Limitations
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* CPU and Processor are BIG-ENDIAN, but this should be no problem as the external memory bus interface provides big- and little-endian configurations
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* CPU and Processor are BIG-ENDIAN, but this should be no problem as the external memory bus interface provides big- and little-endian configurations
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* `misa` CSR is read-only - no dynamic enabling/disabling of synthesized CPU extensions during runtime; for compatibility: write accesses (in m-mode) are ignored and do not cause an exception
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* `misa` CSR is read-only - no dynamic enabling/disabling of synthesized CPU extensions during runtime; for compatibility: write accesses (in m-mode) are ignored and do not cause an exception
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* The physical memory protection (**PMP**) only supports `NAPOT` mode yet and a minimal granularity of 8 bytes
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* The physical memory protection (**PMP**) only supports `NAPOT` mode yet and a minimal granularity of 8 bytes
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* The `A` extension only implements `lr.w` and `sc.w` instructions yet. However, these instructions are sufficient to emulate all further AMO operations
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* The `A` extension only implements `lr.w` and `sc.w` instructions yet. However, these instructions are sufficient to emulate all further AMO operations
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* The `mcause` trap code `0x80000000` (originally reserved in the RISC-V specs) is used to indicate a hardware reset (as "non-maskable interrupt").
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* The `mcause` trap code `0x80000000` (originally reserved in the RISC-V specs) is used to indicate a hardware reset (as "non-maskable interrupt")
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* The bit manipulation extension is not yet officially ratified, but is expected to stay unchanged. There is no software support in the upstream GCC RISC-V port yet. However, an intrinsic library is provided to utilize the provided bit manipulation extension from C-language code (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation)). NEORV32's `B`/`Zbb` extension is compliant to spec. version "0.94-draft".
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### NEORV32-Specific CPU Extensions
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### NEORV32-Specific CPU Extensions
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The NEORV32-specific extensions are always enabled and are indicated via the `X` bit in the `misa` CSR.
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The NEORV32-specific extensions are always enabled and are indicated via the `X` bit in the `misa` CSR.
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| Line 248... |
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a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 20.1** ("balanced implementation"). The timing
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a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 20.1** ("balanced implementation"). The timing
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information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
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information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
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of the CPU's generics is assumed (e.g. no physical memory protection, no hardware performance monitors).
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of the CPU's generics is assumed (e.g. no physical memory protection, no hardware performance monitors).
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No constraints were used at all. The `u` and `Zifencei` extensions have a negligible impact on the hardware requirements.
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No constraints were used at all. The `u` and `Zifencei` extensions have a negligible impact on the hardware requirements.
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Results generated for hardware version [`1.4.9.2`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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Results generated for hardware version [`1.4.9.10`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max |
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| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max |
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|:----------------------------------------|:----------:|:--------:|:-----------:|:----:|:-------:|
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|:-----------------------------------------|:----------:|:--------:|:-----------:|:----:|:-------:|
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| `rv32i` | 1190 | 512 | 2048 | 0 | 120 MHz |
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| `rv32i` | 1190 | 512 | 2048 | 0 | 120 MHz |
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| `rv32i` + `u` + `Zicsr` + `Zifencei` | 1927 | 903 | 2048 | 0 | 123 MHz |
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| `rv32i` + `u` + `Zicsr` + `Zifencei` | 1927 | 903 | 2048 | 0 | 123 MHz |
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| `rv32im` + `u` + `Zicsr` + `Zifencei` | 2471 | 1148 | 2048 | 0 | 120 MHz |
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| `rv32im` + `u` + `Zicsr` + `Zifencei` | 2471 | 1148 | 2048 | 0 | 120 MHz |
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| `rv32imc` + `u` + `Zicsr` + `Zifencei` | 2716 | 1165 | 2048 | 0 | 120 MHz |
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| `rv32imc` + `u` + `Zicsr` + `Zifencei` | 2716 | 1165 | 2048 | 0 | 120 MHz |
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| `rv32imac` + `u` + `Zicsr` + `Zifencei` | 2736 | 1168 | 2048 | 0 | 122 MHz |
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| `rv32imac` + `u` + `Zicsr` + `Zifencei` | 2736 | 1168 | 2048 | 0 | 120 MHz |
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| `rv32imacb` + `u` + `Zicsr` + `Zifencei` | 3045 | 1260 | 2048 | 0 | 114 MHz |
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Setups with enabled "embedded CPU extension" `E` show the same LUT and FF utilization and identical f_max. However, the size of the register file is cut in half.
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Setups with enabled "embedded CPU extension" `E` show the same LUT and FF utilization and identical f_max. However, the size of the register file is cut in half.
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|
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|
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### NEORV32 Processor-Internal Peripherals and Memories
|
### NEORV32 Processor-Internal Peripherals and Memories
|
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Results generated for hardware version [`1.4.9.2`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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Results generated for hardware version [`1.4.9.10`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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| Module | Description | LEs | FFs | Memory bits | DSPs |
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| Module | Description | LEs | FFs | Memory bits | DSPs |
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|:----------|:-----------------------------------------------------|----:|----:|------------:|-----:|
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|:----------|:-----------------------------------------------------|----:|----:|------------:|-----:|
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| BOOT ROM | Bootloader ROM (default 4kB) | 3 | 1 | 32 768 | 0 |
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| BOOT ROM | Bootloader ROM (default 4kB) | 3 | 1 | 32 768 | 0 |
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| BUSSWITCH | Mux for CPU I & D interfaces | 65 | 8 | 0 | 0 |
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| BUSSWITCH | Mux for CPU I & D interfaces | 65 | 8 | 0 | 0 |
|
