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* optional embedded memories (instructions/data/bootloader, RAM/ROM) and caches
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* optional embedded memories (instructions/data/bootloader, RAM/ROM) and caches
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* timers (watch dog, RISC-V-compliant machine timer)
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* timers (watch dog, RISC-V-compliant machine timer)
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* serial interfaces (SPI, TWI, UART)
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* serial interfaces (SPI, TWI, UART)
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* general purpose IO and PWM channels
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* general purpose IO and PWM channels
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* external bus interface (Wishbone / [AXI4](#AXI4-Connectivity))
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* external bus interface (Wishbone / [AXI4](#AXI4-Connectivity))
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* subsystem for custom co-processors
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* [more ...](#NEORV32-Processor-Features)
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* [more ...](#NEORV32-Processor-Features)
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* Software framework
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* Software framework
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* core libraries for high-level usage of the provided functions and peripherals
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* core libraries for high-level usage of the provided functions and peripherals
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* application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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* application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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* GCC-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv-gcc-prebuilt))
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* GCC-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv-gcc-prebuilt))
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### To-Do / Wish List / Help Wanted
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### To-Do / Wish List / Help Wanted
|
|
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* Use LaTeX for data sheet
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* Use LaTeX for data sheet
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* Further size and performance optimization
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* Further size and performance optimization
|
* Further expand associativity configuration of instruction cache (4x/8x set-associativity)
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* Further expand associativity configuration of instruction cache (4x/8x set-associativity)?
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* Add data cache
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* Add data cache?
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* Burst mode for the external memory/bus interface
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* Burst mode for the external memory/bus interface?
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* RISC-V `F` (using [`Zfinx`](https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc)?) CPU extension (single-precision floating point)
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* RISC-V `F` (using [`Zfinx`](https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc)?) CPU extension (single-precision floating point)
|
* Add template (HW module + intrinsics skeleton) for custom instructions?
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* Add template (HW module + intrinsics skeleton) for custom instructions?
|
* Implement further RISC-V (or custom?) CPU extensions
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* Implement further RISC-V (or custom) CPU extensions?
|
* More support for FreeRTOS (like *all* traps)
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* More support for FreeRTOS (like *all* traps)?
|
* Port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))
|
* Port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))?
|
* Maybe port [CircuitPython](https://circuitpython.org/) (just for fun)
|
* Add debugger ([RISC-V debug spec](https://github.com/riscv/riscv-debug-spec))?
|
* Add debugger ([RISC-V debug spec](https://github.com/riscv/riscv-debug-spec))
|
* Add encryption/decryption/hash accelerator (maybe [XTEA](https://en.wikipedia.org/wiki/XTEA))?
|
* ...
|
* ...
|
* [Ideas?](#ContributeFeedbackQuestions)
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* [Ideas?](#ContributeFeedbackQuestions)
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|
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|
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#### NEORV32-specific CPU extensions (`X` extension)
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#### NEORV32-specific CPU extensions (`X` extension)
|
|
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* The NEORV32-specific extensions are always enabled and are indicated via the `X` bit set in the `misa` CSR.
|
* The NEORV32-specific extensions are always enabled and are indicated via the `X` bit set in the `misa` CSR.
|
* Eight *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause`
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* 16 *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause`
|
* `mzext` CSR to check for implemented `Z*` CPU extensions (like `Zifencei`)
|
* `mzext` CSR to check for implemented `Z*` CPU extensions (like `Zifencei`)
|
* All undefined/umimplemented/malformed/illegal instructions do raise an illegal instruction exception
|
* All undefined/umimplemented/malformed/illegal instructions do raise an illegal instruction exception
|
|
|
|
|
#### Privileged architecture - CSR access (`Zicsr` extension)
|
#### Privileged architecture - CSR access (`Zicsr` extension)
|
