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[](https://github.com/stnolting/neorv32)
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[](https://github.com/stnolting/neorv32)
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# The NEORV32 RISC-V Processor
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# The NEORV32 RISC-V Processor
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22RISC-V+Compliance%22)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22RISC-V+Compliance%22)
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:page_facing_up: For more detailed information take a look at the [NEORV32 data sheet (pdf)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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:page_facing_up: For more detailed information take a look at the [NEORV32 data sheet (pdf)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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### Key Features
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### Key Features
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* RISC-V 32-bit `rv32i` [**NEORV32 CPU**](#NEORV32-CPU-Features), compliant to
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* RISC-V 32-bit `rv32` [**NEORV32 CPU**](#NEORV32-CPU-Features), compliant to
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* subset of the *Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf)
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* subset of the *Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf)
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* subset of the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf)
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* subset of the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf)
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* the [offcial RISC-V compliance tests](#Status) (*passing*)
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* the [official RISC-V compliance tests](#Status) (*passing*)
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* Configurable RISC-V-compliant CPU extensions
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* Configurable RISC-V-compliant CPU extensions
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* [`A`](#Atomic-memory-access-a-extension) - atomic memory access instructions (optional)
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* [`A`](#Atomic-memory-access-a-extension) - atomic memory access instructions (optional)
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* [`B`](#Bit-manipulation-instructions-B-extension) - Bit manipulation instructions (optional)
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* [`B`](#Bit-manipulation-instructions-B-extension) - Bit manipulation instructions (optional)
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* [`C`](#Compressed-instructions-C-extension) - compressed instructions (16-bit) (optional)
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* [`C`](#Compressed-instructions-C-extension) - compressed instructions (16-bit) (optional)
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* [`E`](#Embedded-CPU-version-E-extension) - embedded CPU (reduced register file size) (optional)
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* [`E`](#Embedded-CPU-version-E-extension) - embedded CPU (reduced register file size) (optional)
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* [`PMP`](#Privileged-architecture---Physical-memory-protection-PMP) - physical memory protection (optional)
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* [`PMP`](#Privileged-architecture---Physical-memory-protection-PMP) - physical memory protection (optional)
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* [`HPM`](#Privileged-architecture---Hardware-performance-monitors-HPM-extension) - hardware performance monitors (optional)
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* [`HPM`](#Privileged-architecture---Hardware-performance-monitors-HPM-extension) - hardware performance monitors (optional)
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* Full-scale RISC-V microcontroller system / **SoC** [**NEORV32 Processor**](#NEORV32-Processor-Features) with optional submodules
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* Full-scale RISC-V microcontroller system / **SoC** [**NEORV32 Processor**](#NEORV32-Processor-Features) with optional submodules
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* optional embedded memories (instructions/data/bootloader, RAM/ROM) and caches
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* optional embedded memories (instructions/data/bootloader, RAM/ROM) and caches
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* timers (watch dog, RISC-V-compliant machine timer)
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* timers (watch dog, RISC-V-compliant machine timer)
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* serial interfaces (SPI, TWI, UART)
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* serial interfaces (SPI, TWI, UARTs)
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* general purpose IO and PWM channels
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* general purpose IO and PWM channels
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* external bus interface (Wishbone / [AXI4](#AXI4-Connectivity))
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* external bus interface (Wishbone / [AXI4](#AXI4-Connectivity))
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* subsystem for custom co-processors
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* subsystem for custom co-processors
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* [more ...](#NEORV32-Processor-Features)
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* [more ...](#NEORV32-Processor-Features)
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* Software framework
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* Software framework
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* Further size and performance optimization
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* Further size and performance optimization
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* Further expand associativity configuration of instruction cache (4x/8x set-associativity)?
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* Further expand associativity configuration of instruction cache (4x/8x set-associativity)?
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* Add data cache?
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* Add data cache?
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* Burst mode for the external memory/bus interface?
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* Burst mode for the external memory/bus interface?
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* RISC-V `F` (using [`Zfinx`](https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc)?) CPU extension (single-precision floating point)
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* RISC-V `F` (using [`Zfinx`](https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc)?) CPU extension (single-precision floating point)
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* RISC-V `K` CPU extension: [Crypto](https://github.com/riscv/riscv-crypto)
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* Add template (HW module + SW intrinsics skeleton) for custom instructions?
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* Add template (HW module + SW intrinsics skeleton) for custom instructions?
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* Implement further RISC-V CPU extensions?
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* Implement further RISC-V CPU extensions?
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* More support for FreeRTOS (like *all* traps)?
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* More support for FreeRTOS?
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* Port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))?
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* Port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))?
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* Add debugger ([RISC-V debug spec](https://github.com/riscv/riscv-debug-spec))?
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* Add debugger ([RISC-V debug spec](https://github.com/riscv/riscv-debug-spec))?
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* Add encryption/decryption/hash accelerator (maybe [XTEA](https://en.wikipedia.org/wiki/XTEA))?
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* ...
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* ...
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* [Ideas?](#ContributeFeedbackQuestions)
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* [Ideas?](#ContributeFeedbackQuestions)
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* processor-internal data and instruction memories (**DMEM** / **IMEM**) & cache (**iCACHE**)
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* processor-internal data and instruction memories (**DMEM** / **IMEM**) & cache (**iCACHE**)
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* bootloader (**BOOTLDROM**) with UART console and automatic application boot from SPI flash option
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* bootloader (**BOOTLDROM**) with UART console and automatic application boot from SPI flash option
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* machine system timer (**MTIME**), RISC-V-compliant
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* machine system timer (**MTIME**), RISC-V-compliant
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* watchdog timer (**WDT**)
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* watchdog timer (**WDT**)
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* universal asynchronous receiver and transmitter (**UART**) with simulation output option via text.io
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* two independent universal asynchronous receiver and transmitter (**UART0** & **UART1**) with fast simulation output option
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* 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines
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* 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines
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* two wire serial interface controller (**TWI**), with optional clock-stretching, compatible to the I²C standard
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* two wire serial interface controller (**TWI**), with optional clock-stretching, compatible to the I²C standard
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* general purpose parallel IO port (**GPIO**), 32xOut & 32xIn, with pin-change interrupt
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* general purpose parallel IO port (**GPIO**), 32xOut & 32xIn, with pin-change interrupt
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* 32-bit external bus interface, Wishbone b4 compliant (**WISHBONE**), *standard* or *pipelined* handshake/transactions mode
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* 32-bit external bus interface, Wishbone b4 compliant (**WISHBONE**), *standard* or *pipelined* handshake/transactions mode
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* wrapper for **AXI4-Lite Master Interface** (see [AXI Connectivity](#AXI4-Connectivity))
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* wrapper for **AXI4-Lite Master Interface** (see [AXI Connectivity](#AXI4-Connectivity))
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| PWM | Pulse-width modulation controller | 71 | 69 | 0 | 0 |
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| PWM | Pulse-width modulation controller | 71 | 69 | 0 | 0 |
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| SPI | Serial peripheral interface | 138 | 124 | 0 | 0 |
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| SPI | Serial peripheral interface | 138 | 124 | 0 | 0 |
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| SYSINFO | System configuration information memory | 11 | 10 | 0 | 0 |
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| SYSINFO | System configuration information memory | 11 | 10 | 0 | 0 |
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| TRNG | True random number generator | 132 | 105 | 0 | 0 |
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| TRNG | True random number generator | 132 | 105 | 0 | 0 |
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| TWI | Two-wire interface | 77 | 46 | 0 | 0 |
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| TWI | Two-wire interface | 77 | 46 | 0 | 0 |
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| UART | Universal asynchronous receiver/transmitter | 176 | 132 | 0 | 0 |
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| UART0/1 | Universal asynchronous receiver/transmitter 0/1 | 176 | 132 | 0 | 0 |
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| WDT | Watchdog timer | 60 | 45 | 0 | 0 |
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| WDT | Watchdog timer | 60 | 45 | 0 | 0 |
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| WISHBONE | External memory interface | 129 | 104 | 0 | 0 |
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| WISHBONE | External memory interface | 129 | 104 | 0 | 0 |
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### NEORV32 Processor - Exemplary FPGA Setups
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### NEORV32 Processor - Exemplary FPGA Setups
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This overview is just a short excerpt from the *Let's Get It Started* section of the NEORV32 documentary:
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This overview is just a short excerpt from the *Let's Get It Started* section of the NEORV32 documentary:
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[:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf)
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[:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf)
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### Toolchain
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### 1. Get Toolchain
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At first you need the **RISC-V GCC toolchain**. You can either [download the sources](https://github.com/riscv/riscv-gnu-toolchain)
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At first you need a **RISC-V GCC toolchain**. You can either [download the sources](https://github.com/riscv/riscv-gnu-toolchain)
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and build the toolchain by yourself, or you can download a prebuilt one and install it.
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and build the toolchain by yourself, or you can download a prebuilt one and install it.
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To build the toolchain by yourself, follow the official [build instructions](https://github.com/riscv/riscv-gnu-toolchain).
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To build the toolchain by yourself, follow the official [build instructions](https://github.com/riscv/riscv-gnu-toolchain).
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Make sure to use the `ilp32` or `ilp32e` ABI.
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Make sure to use the `ilp32` or `ilp32e` ABI.
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**Alternatively**, you can download a prebuilt toolchain. I have uploaded the toolchains I am using to GitHub. These toolchains
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**Alternatively**, you can download a prebuilt toolchain. I have uploaded the toolchains I am using to GitHub. These toolchains
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were compiled on a 64-bit x86 Ubuntu 20.04 LTS (Ubuntu on Windows, actually). Download the toolchain of choice:
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were compiled on a 64-bit x86 Ubuntu 20.04 LTS (Ubuntu on Windows, actually). Download the toolchain of choice:
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[:octocat: github.com/stnolting/riscv-gcc-prebuilt](https://github.com/stnolting/riscv-gcc-prebuilt)
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[:octocat: github.com/stnolting/riscv-gcc-prebuilt](https://github.com/stnolting/riscv-gcc-prebuilt)
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You can also use the toolchains provided by [SiFive](https://github.com/sifive/freedom-tools/releases). These are 64-bit toolchains that can also emit 32-bit
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You can also use the toolchains provided by [SiFive](https://github.com/sifive/freedom-tools/releases). These are 64-bit toolchains that can also emit 32-bit
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RISC-V code. They were compiled for more sophisticated machines (`imac`) so the according hardware extensions are *mandatory*
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RISC-V code. They were compiled for more sophisticated machines (`rv32imac`) so make sure the according NEORV32 hardware extensions are enabled.
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:warning: Keep in mind that – for instance – a `rv32imc` toolchain only provides library code compiled with compressed and
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:warning: Keep in mind that – for instance – a `rv32imc` toolchain only provides library code compiled with compressed and
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`mul`/`div` instructions! Hence, this code cannot be executed (without emulation) on an architecture without these extensions!
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`mul`/`div` instructions! Hence, this code cannot be executed (without emulation) on an architecture without these extensions!
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To check everything works fine, make sure `GNU Make` and a native `GCC` compiler are installed.
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Test the installation of the RISC-V toolchain by navigating to an [example program project](https://github.com/stnolting/neorv32/tree/master/sw/example) like
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`sw/example/blink_led` and running:
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neorv32/sw/example/blink_led$ make check
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### Dowload the NEORV32 Project
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### 2. Dowload the NEORV32 Project
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Get the sources of the NEORV32 Processor project. The simplest way is using `git clone` (suggested for easy project updates via `git pull`):
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Get the sources of the NEORV32 Processor project. The simplest way is using `git clone` (suggested for easy project updates via `git pull`):
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$ git clone https://github.com/stnolting/neorv32.git
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$ git clone https://github.com/stnolting/neorv32.git
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Alternatively, you can either download a specific [release](https://github.com/stnolting/neorv32/releases) or get the most recent version
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Alternatively, you can either download a specific [release](https://github.com/stnolting/neorv32/releases) or get the most recent version
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of this project as [`*.zip` file](https://github.com/stnolting/neorv32/archive/master.zip).
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of this project as [`*.zip` file](https://github.com/stnolting/neorv32/archive/master.zip).
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### Create a new Hardware Project
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### 3. Create a new Hardware Project
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Create a new project with your FPGA design tool of choice. Add all the `*.vhd` files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl)
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Create a new project with your FPGA design tool of choice. Add all the `*.vhd` files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl)
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folder to this project. Make sure to add these files to a **new design library** called `neorv32`.
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folder to this project. Make sure to add these files to a **new design library** called `neorv32`.
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You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) or one of its
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You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) or one of its
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you can use the simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) as top entity.
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you can use the simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) as top entity.
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This test setup instantiates the processor and implements most of the peripherals and some ISA extensions. Only the UART lines, clock, reset and some GPIO output signals are
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This test setup instantiates the processor and implements most of the peripherals and some ISA extensions. Only the UART0 lines, clock, reset and some GPIO output signals are
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propagated as actual entity signals. Basically, it is a FPGA "hello world" example:
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propagated as actual entity signals. Basically, it is a FPGA "hello world" example:
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```vhdl
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```vhdl
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entity neorv32_test_setup is
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entity neorv32_test_setup is
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port (
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port (
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-- Global control --
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-- Global control --
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clk_i : in std_ulogic := '0'; -- global clock, rising edge
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clk_i : in std_ulogic := '0'; -- global clock, rising edge
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rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
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rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
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-- GPIO --
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-- GPIO --
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gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output
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gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output
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-- UART --
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-- UART0 --
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uart_txd_o : out std_ulogic; -- UART send data
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uart0_txd_o : out std_ulogic; -- UART0 send data
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uart_rxd_i : in std_ulogic := '0' -- UART receive data
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uart0_rxd_i : in std_ulogic := '0' -- UART0 receive data
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);
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);
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end neorv32_test_setup;
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end neorv32_test_setup;
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```
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```
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### Check the Toolchain
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### 4. Compile an Example Program
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Make sure `GNU Make` and a native `GCC` compiler are installed. To test the installation of the RISC-V toolchain navigate to an example project like
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`sw/example/blink_led` and run:
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neorv32/sw/example/blink_led$ make check
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The NEORV32 project includes several [example program project](https://github.com/stnolting/neorv32/tree/master/sw/example) from
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which you can start your own application. There are example programs to check out the processor's peripheral like I2C or the true-random number generator.
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And yes, there is also a port of [Conway's Game of Life](https://github.com/stnolting/neorv32/tree/master/sw/example/game_of_life) available! :wink:
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### Compiling an Example Program
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Simply compile one of these projects using
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The NEORV32 project includes some [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) from
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which you can start your own application. Simply compile one of these projects. This will create a NEORV32
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*executable* `neorv32_exe.bin` in the same folder:
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neorv32/sw/example/blink_led$ make clean_all exe
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neorv32/sw/example/blink_led$ make clean_all exe
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This will create a NEORV32 *executable* `neorv32_exe.bin` in the same folder, which you can upload via the bootloader.
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### Upload the Executable via the Bootloader
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You can upload a generated executable directly from the command line using the makefile's `upload` target. Replace `/dev/ttyUSB0` with
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the according serial port.
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sw/exeample/blink_example$ make COM_PORT=/dev/ttyUSB0` upload
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### 5. Upload the Executable via the Bootloader
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A more "secure" way is to use a dedicated terminal program. This allows to directly interact with the bootloader console.
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Connect your FPGA board via UART to your computer and open the according port to interface with the fancy NEORV32 bootloader. The bootloader
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Connect your FPGA board via UART to your computer and open the according port to interface with the NEORV32 bootloader. The bootloader
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uses the following default UART configuration:
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uses the following default UART configuration:
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* 19200 Baud
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* 19200 Baud
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* 8 data bits
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* 8 data bits
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* 1 stop bit
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* 1 stop bit
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* No parity bits
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* No parity bits
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* No transmission / flow control protocol (raw bytes only)
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* No transmission / flow control protocol (raw bytes only)
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* Newline on `\r\n` (carriage return & newline) - also for sent data
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* Newline on `\r\n` (carriage return & newline) - also for sent data
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Use the bootloader console to upload the `neorv32_exe.bin` executable and run your application image.
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Use the bootloader console to upload the `neorv32_exe.bin` executable gerated during application compiling and run your application.
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```
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```
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<< NEORV32 Bootloader >>
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<< NEORV32 Bootloader >>
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BLDV: Nov 7 2020
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BLDV: Nov 7 2020
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