| Line 61... |
Line 61... |
* optional embedded memories (instructions/data/bootloader, RAM/ROM) and caches
|
* optional embedded memories (instructions/data/bootloader, RAM/ROM) and caches
|
* timers (watch dog, RISC-V-compatible machine timer)
|
* timers (watch dog, RISC-V-compatible machine timer)
|
* serial interfaces (SPI, TWI, UARTs)
|
* serial interfaces (SPI, TWI, UARTs)
|
* general purpose IO and PWM channels
|
* general purpose IO and PWM channels
|
* external bus interface (Wishbone / [AXI4](#AXI4-Connectivity))
|
* external bus interface (Wishbone / [AXI4](#AXI4-Connectivity))
|
* dedicated NeoPixel(c) LED interface
|
* dedicated NeoPixel(TM) LED interface
|
* subsystem for custom co-processors
|
* subsystem for custom co-processors
|
* [more ...](#NEORV32-Processor-Features)
|
* [more ...](#NEORV32-Processor-Features)
|
* Software framework
|
* Software framework
|
* core libraries for high-level usage of the provided functions and peripherals
|
* core libraries for high-level usage of the provided functions and peripherals
|
* application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
|
* application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
|
| Line 168... |
Line 168... |
* Supported instructions: `LR.W` (load-reservate) `SC.W` (store-conditional)
|
* Supported instructions: `LR.W` (load-reservate) `SC.W` (store-conditional)
|
|
|
|
|
#### `B` - Bit manipulation instructions extension
|
#### `B` - Bit manipulation instructions extension
|
|
|
* :construction: **WORK-IN-PROGRESS** :construction:
|
* :construction: **work-in-progress** :construction:
|
* :warning: The bit-manipulation extension has not been officially ratified yet!
|
* :warning: this extension has not been officially ratified yet!
|
|
* :books: more information can be found here: [RISC-V `B` spec.](https://github.com/riscv/riscv-bitmanip)
|
* Compatible to [v0.94-draft](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/bitmanip-draft.pdf) of the bit manipulation spec
|
* Compatible to [v0.94-draft](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/bitmanip-draft.pdf) of the bit manipulation spec
|
* Support via intrisc library (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation))
|
* Support via intrisc library (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation))
|
* `Zbb` base instruction set: `CLZ` `CTZ` `CPOP` `SEXT.B` `SEXT.H` `MIN[U]` `MAX[U]` `ANDN` `ORN` `XNOR` `ROL` `ROR[I]` `zext`(*pseudo-instruction* for `PACK rd, rs, zero`) `rev8`(*pseudo-instruction* for `GREVI rd, rs, -8`) `orc.b`(*pseudo-instruction* for `GORCI rd, rs, 7`)
|
* `Zbb` base instruction set: `CLZ` `CTZ` `CPOP` `SEXT.B` `SEXT.H` `MIN[U]` `MAX[U]` `ANDN` `ORN` `XNOR` `ROL` `ROR[I]` `zext`(*pseudo-instruction* for `PACK rd, rs, zero`) `rev8`(*pseudo-instruction* for `GREVI rd, rs, -8`) `orc.b`(*pseudo-instruction* for `GORCI rd, rs, 7`)
|
* `Zbs` single-bit instructions: `SBSET[I]` `SBCLR[I]` `SBINV[I]` `SBEXT[I]`
|
* `Zbs` single-bit instructions: `SBSET[I]` `SBCLR[I]` `SBINV[I]` `SBEXT[I]`
|
|
* `Zba` shifted-add instructions: `SH1ADD` `SH2ADD` `SH3ADD`
|
|
|
|
|
#### `C` - Compressed instructions extension
|
#### `C` - Compressed instructions extension
|
|
|
* ALU instructions: `C.ADDI4SPN` `C.ADD[I]` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP`
|
* ALU instructions: `C.ADDI4SPN` `C.ADD[I]` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP`
|
* Jump and branch instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ`
|
* Jump and branch instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ`
|
* Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP`
|
* Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP`
|
* System instructions: `C.EBREAK` (requires `Zicsr` extension)
|
* System instructions: `C.EBREAK` (requires `Zicsr` extension)
|
* Floating-point instructions: `C.FLW` `C.FSW` `C.FLWSP` `C.FSWSP` (requires `F` extension)
|
|
* Pseudo-instructions are not listed
|
* Pseudo-instructions are not listed
|
|
|
#### `E` - Embedded CPU version extension
|
#### `E` - Embedded CPU version extension
|
|
|
* Reduced register file (only the 16 lowest registers are implemented)
|
* Reduced register file (only the 16 lowest registers are implemented)
|
|
|
|
|
#### `F` - Single-precision floating-point extension
|
|
|
|
* :construction: **WORK-IN-PROGRESS** :construction:
|
|
* :warning: the `F` extension is not operational yet!
|
|
* :information_source: check out the [F-extension project board](https://github.com/stnolting/neorv32/projects/4) for the current implementation state
|
|
|
|
|
|
#### `I` - Base integer instruction set
|
#### `I` - Base integer instruction set
|
|
|
* ALU instructions: `LUI` `AUIPC` `ADD[I]` `SLT[I][U]` `XOR[I]` `OR[I]` `AND[I]` `SLL[I]` `SRL[I]` `SRA[I]` `SUB`
|
* ALU instructions: `LUI` `AUIPC` `ADD[I]` `SLT[I][U]` `XOR[I]` `OR[I]` `AND[I]` `SLL[I]` `SRL[I]` `SRA[I]` `SUB`
|
* Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
|
* Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
|
* Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW`
|
* Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW`
|
| Line 228... |
Line 222... |
* 16 *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause`
|
* 16 *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause`
|
* `mzext` CSR to check for implemented `Z*` CPU extensions (like `Zifencei`)
|
* `mzext` CSR to check for implemented `Z*` CPU extensions (like `Zifencei`)
|
* All undefined/umimplemented/malformed/illegal instructions do raise an illegal instruction exception
|
* All undefined/umimplemented/malformed/illegal instructions do raise an illegal instruction exception
|
|
|
|
|
|
#### `Zfinx` - Single-precision floating-point extension (using integer `x` registers)
|
|
|
|
* :construction: **work-in-progress** :construction:
|
|
* :warning: this extension has not been officially ratified yet!
|
|
* :books: more information can be found here: [RISC-V `Zfinx` spec.](https://github.com/riscv/riscv-zfinx)
|
|
* :information_source: check out the [floating-point extension project board](https://github.com/stnolting/neorv32/projects/4) for the current implementation state
|
|
|
|
|
#### `Zicsr` - Privileged architecture - CSR access extension
|
#### `Zicsr` - Privileged architecture - CSR access extension
|
|
|
* Privilege levels: `M-mode` (Machine mode)
|
* Privilege levels: `M-mode` (Machine mode)
|
* CSR access instructions: `CSRRW[I]` `CSRRS[I]` `CSRRC[I]`
|
* CSR access instructions: `CSRRW[I]` `CSRRS[I]` `CSRRC[I]`
|
* System instructions: `MRET` `WFI`
|
* System instructions: `MRET` `WFI`
|
