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## Overview
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## Overview
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based
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on the RISC-V NEORV32 CPU. The processor is intended as *ready-to-go* auxiliary processor within a larger SoC
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on the RISC-V NEORV32 CPU. The processor is intended as *ready-to-go* auxiliary processor within a larger SoC
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designs or as stand-alone custom microcontroller.
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designs or as stand-alone custom microcontroller.
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:books: For detailed information take a look at the [NEORV32 data sheet (pdf)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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:books: For detailed information take a look at the [NEORV32 data sheet (pdf)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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[:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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[:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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### NEORV32 Processor Features
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### NEORV32 Processor Features
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The NEORV32 Processor provides a full-scale microcontroller-like SoC based on the NEORV32 CPU. The setup
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The NEORV32 Processor provides a full-scale microcontroller-like SoC based on the NEORV32 CPU. The setup
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is highly customizable via the processor's top generics and already provides the following *optional* modules:
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is highly customizable via the processor's top generics and already provides the following *optional* modules:
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* processor-internal data and instruction memories (**DMEM** / **IMEM**) & cache (**iCACHE**)
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* processor-internal data and instruction memories (**DMEM** / **IMEM**) & cache (**iCACHE**)
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* bootloader (**BOOTLDROM**) with UART console and automatic application boot from SPI flash option
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* bootloader (**BOOTLDROM**) with UART console and automatic application boot from SPI flash option
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* :construction: **work-in-progress** :construction:
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* :construction: **work-in-progress** :construction:
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* :warning: this extension has not been officially ratified yet!
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* :warning: this extension has not been officially ratified yet!
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* :books: more information can be found here: [RISC-V `B` spec.](https://github.com/riscv/riscv-bitmanip)
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* :books: more information can be found here: [RISC-V `B` spec.](https://github.com/riscv/riscv-bitmanip)
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* Compatible to [v0.94-draft](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/bitmanip-draft.pdf) of the bit manipulation spec
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* Compatible to [v0.94-draft](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/bitmanip-draft.pdf) of the bit manipulation spec
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* Support via intrisc library (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation))
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* Support via intrinsic library (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation))
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* `Zbb` base instruction set: `CLZ` `CTZ` `CPOP` `SEXT.B` `SEXT.H` `MIN[U]` `MAX[U]` `ANDN` `ORN` `XNOR` `ROL` `ROR[I]` `zext`(*pseudo-instruction* for `PACK rd, rs, zero`) `rev8`(*pseudo-instruction* for `GREVI rd, rs, -8`) `orc.b`(*pseudo-instruction* for `GORCI rd, rs, 7`)
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* `Zbb` base instruction set: `CLZ` `CTZ` `CPOP` `SEXT.B` `SEXT.H` `MIN[U]` `MAX[U]` `ANDN` `ORN` `XNOR` `ROL` `ROR[I]` `zext`(*pseudo-instruction* for `PACK rd, rs, zero`) `rev8`(*pseudo-instruction* for `GREVI rd, rs, -8`) `orc.b`(*pseudo-instruction* for `GORCI rd, rs, 7`)
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* `Zbs` single-bit instructions: `SBSET[I]` `SBCLR[I]` `SBINV[I]` `SBEXT[I]`
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* `Zbs` single-bit instructions: `SBSET[I]` `SBCLR[I]` `SBINV[I]` `SBEXT[I]`
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* `Zba` shifted-add instructions: `SH1ADD` `SH2ADD` `SH3ADD`
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* `Zba` shifted-add instructions: `SH1ADD` `SH2ADD` `SH3ADD`
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