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## Overview
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## Overview
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based
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on the RISC-V NEORV32 CPU. The processor is intended as *ready-to-go* auxiliary processor within a larger SoC
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on the RISC-V NEORV32 CPU. The processor is intended as auxiliary processor within a larger SoC
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designs or as stand-alone custom microcontroller.
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designs or as *ready-to-go* stand-alone custom microcontroller.
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:books: For detailed information take a look at the [NEORV32 data sheet (pdf)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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:books: For detailed information take a look at the [NEORV32 data sheet (pdf)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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The doxygen-based documentation of the *software framework* is available online at [GitHub-pages](https://stnolting.github.io/neorv32/files.html).
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The doxygen-based documentation of the *software framework* is available online at [GitHub-pages](https://stnolting.github.io/neorv32/files.html).
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:label: The project’s change log is available as [CHANGELOG.md](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) in the root directory of this repository.
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:label: The project’s change log is available as [CHANGELOG.md](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) in the root directory of this repository.
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* [`E`](#E---Embedded-CPU-version-extension) - embedded CPU (reduced register file size) (optional)
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* [`E`](#E---Embedded-CPU-version-extension) - embedded CPU (reduced register file size) (optional)
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* [`I`](#I---Base-integer-instruction-set) - base integer instruction set (always enabled)
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* [`I`](#I---Base-integer-instruction-set) - base integer instruction set (always enabled)
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* [`M`](#M---Integer-multiplication-and-division-hardware-extension) - integer multiplication and division hardware (optional)
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* [`M`](#M---Integer-multiplication-and-division-hardware-extension) - integer multiplication and division hardware (optional)
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* [`U`](#U---Privileged-architecture---User-mode-extension) - less-privileged *user mode* (optional)
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* [`U`](#U---Privileged-architecture---User-mode-extension) - less-privileged *user mode* (optional)
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* [`X`](#X---NEORV32-specific-CPU-extensions) - NEORV32-specific extensions (always enabled)
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* [`X`](#X---NEORV32-specific-CPU-extensions) - NEORV32-specific extensions (always enabled)
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* [`Zfinx`](#Zfinx---Single-precision-floating-point-extension) - Single-precision floating-point extensions (optional)
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* [`Zicsr`](#Zicsr---Privileged-architecture---CSR-access-extension) - control and status register access instructions (+ exception/irq system) (optional)
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* [`Zicsr`](#Zicsr---Privileged-architecture---CSR-access-extension) - control and status register access instructions (+ exception/irq system) (optional)
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* [`Zifencei`](#Zifencei---Privileged-architecture---Instruction-stream-synchronization-extension) - instruction stream synchronization (optional)
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* [`Zifencei`](#Zifencei---Privileged-architecture---Instruction-stream-synchronization-extension) - instruction stream synchronization (optional)
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* [`PMP`](#PMP---Privileged-architecture---Physical-memory-protection) - physical memory protection (optional)
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* [`PMP`](#PMP---Privileged-architecture---Physical-memory-protection) - physical memory protection (optional)
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* [`HPM`](#HPM---Privileged-architecture---Hardware-performance-monitors) - hardware performance monitors (optional)
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* [`HPM`](#HPM---Privileged-architecture---Hardware-performance-monitors) - hardware performance monitors (optional)
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* Full-scale RISC-V microcontroller system / **SoC** [**NEORV32 Processor**](#NEORV32-Processor-Features) with optional submodules
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* Full-scale RISC-V microcontroller system / **SoC** [**NEORV32 Processor**](#NEORV32-Processor-Features) with optional submodules
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| Line 73... |
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* application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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* application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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* GCC-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv-gcc-prebuilt))
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* GCC-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv-gcc-prebuilt))
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* bootloader with UART interface console
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* bootloader with UART interface console
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* runtime environment
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* runtime environment
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* several example programs
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* several example programs
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* [doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) software documentation: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)
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* [doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/Doxyfile) software documentation: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)
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* [FreeRTOS port](https://github.com/stnolting/neorv32/blob/master/sw/example/demo_freeRTOS) available
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* [FreeRTOS port](https://github.com/stnolting/neorv32/blob/master/sw/example/demo_freeRTOS) available
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* [**Full-blown data sheet**](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)
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* [**Full-blown data sheet**](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)
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* Completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
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* Completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
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* Fully synchronous design, no latches, no gated clocks
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* Fully synchronous design, no latches, no gated clocks
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* Small hardware footprint and high operating frequency
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* Small hardware footprint and high operating frequency
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| Line 172... |
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* :construction: **work-in-progress** :construction:
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* :construction: **work-in-progress** :construction:
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* :warning: this extension has not been officially ratified yet!
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* :warning: this extension has not been officially ratified yet!
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* :books: more information can be found here: [RISC-V `B` spec.](https://github.com/riscv/riscv-bitmanip)
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* :books: more information can be found here: [RISC-V `B` spec.](https://github.com/riscv/riscv-bitmanip)
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* Compatible to [v0.94-draft](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/bitmanip-draft.pdf) of the bit manipulation spec
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* Compatible to [v0.94-draft](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/bitmanip-draft.pdf) of the bit manipulation spec
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* Support via intrinsic library (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation))
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* Software support via intrinsic library (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation))
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* `Zbb` base instruction set: `CLZ` `CTZ` `CPOP` `SEXT.B` `SEXT.H` `MIN[U]` `MAX[U]` `ANDN` `ORN` `XNOR` `ROL` `ROR[I]` `zext`(*pseudo-instruction* for `PACK rd, rs, zero`) `rev8`(*pseudo-instruction* for `GREVI rd, rs, -8`) `orc.b`(*pseudo-instruction* for `GORCI rd, rs, 7`)
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* `Zbb` base instruction set: `CLZ` `CTZ` `CPOP` `SEXT.B` `SEXT.H` `MIN[U]` `MAX[U]` `ANDN` `ORN` `XNOR` `ROL` `ROR[I]` `zext`(*pseudo-instruction* for `PACK rd, rs, zero`) `rev8`(*pseudo-instruction* for `GREVI rd, rs, -8`) `orc.b`(*pseudo-instruction* for `GORCI rd, rs, 7`)
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* `Zbs` single-bit instructions: `SBSET[I]` `SBCLR[I]` `SBINV[I]` `SBEXT[I]`
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* `Zbs` single-bit instructions: `SBSET[I]` `SBCLR[I]` `SBINV[I]` `SBEXT[I]`
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* `Zba` shifted-add instructions: `SH1ADD` `SH2ADD` `SH3ADD`
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* `Zba` shifted-add instructions: `SH1ADD` `SH2ADD` `SH3ADD`
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| Line 222... |
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* 16 *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause`
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* 16 *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause`
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* `mzext` CSR to check for implemented `Z*` CPU extensions (like `Zifencei`)
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* `mzext` CSR to check for implemented `Z*` CPU extensions (like `Zifencei`)
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* All undefined/umimplemented/malformed/illegal instructions do raise an illegal instruction exception
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* All undefined/umimplemented/malformed/illegal instructions do raise an illegal instruction exception
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#### `Zfinx` - Single-precision floating-point extension (using integer `x` registers)
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#### `Zfinx` - Single-precision floating-point extension
|
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* :construction: **work-in-progress** :construction:
|
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* :warning: this extension has not been officially ratified yet!
|
* :warning: this extension has not been officially ratified yet!
|
* :books: more information can be found here: [RISC-V `Zfinx` spec.](https://github.com/riscv/riscv-zfinx)
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* :books: more information can be found here: [RISC-V `Zfinx` spec.](https://github.com/riscv/riscv-zfinx)
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* :information_source: check out the [floating-point extension project board](https://github.com/stnolting/neorv32/projects/4) for the current implementation state
|
* Software support via intrinsic library (see [`sw/example/floating_point_test`](https://github.com/stnolting/neorv32/tree/master/sw/example/floating_point_test))
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* Fused multiply-add instructions (`F[N]MADD.S` & `F[N)MSUB.S`) are **not** supported!
|
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* Computational instructions: `FADD.S` `FSUB.S` `FMUL.S` `FSGNJ[N/X].S` `FCLASS.S` ~~`FDIV.S`~~ ~~`FSQRT.S`~~
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* Comparison instructions: `FMIN.S` `FMAX.S` `FEQ.S` `FLT.S` `FLE.S`
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* Conversion instructions: `FCVT.W.S` `FCVT.WU.S` `FCVT.S.W` `FCVT.S.WU`
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* Additional CSRs: `fcsr` `frm` `fflags`
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#### `Zicsr` - Privileged architecture - CSR access extension
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#### `Zicsr` - Privileged architecture - CSR access extension
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* Privilege levels: `M-mode` (Machine mode)
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* Privilege levels: `M-mode` (Machine mode)
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| Line 249... |
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* Load access fault (via timeout/error after unacknowledged bus access)
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* Load access fault (via timeout/error after unacknowledged bus access)
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* Store address misaligned
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* Store address misaligned
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* Store access fault (via unacknowledged bus access after timeout)
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* Store access fault (via unacknowledged bus access after timeout)
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* Environment call from U-mode (via `ecall` instruction in user mode)
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* Environment call from U-mode (via `ecall` instruction in user mode)
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* Environment call from M-mode (via `ecall` instruction in machine mode)
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* Environment call from M-mode (via `ecall` instruction in machine mode)
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* Supported (async.) exceptions / interrupts:
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* Supported interrupts:
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* Machine timer interrupt `mti` (via processor's MTIME unit / external signal)
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* RISC-V machine timer interrupt `mti` (via processor-internal MTIME unit *or* external signal)
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* Machine software interrupt `msi` (via external signal)
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* RISC-V machine software interrupt `msi` (via external signal)
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* Machine external interrupt `mei` (via external signal)
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* RISC-V machine external interrupt `mei` (via external signal)
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* 16 fast interrupt requests (custom extension), 6+1 available for custom usage
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* 16 fast interrupt requests, 6+1 available for custom usage
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#### `Zifencei` - Privileged architecture - Instruction stream synchronization extension
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#### `Zifencei` - Privileged architecture - Instruction stream synchronization extension
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* System instructions: `FENCE.I` (among others, used to clear and reload instruction cache)
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* System instructions: `FENCE.I` (among others, used to clear and reload instruction cache)
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* CPU and Processor are BIG-ENDIAN, but this should be no problem as the external memory bus interface provides big- and little-endian configurations
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* CPU and Processor are BIG-ENDIAN, but this should be no problem as the external memory bus interface provides big- and little-endian configurations
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* `misa` CSR is read-only - no dynamic enabling/disabling of synthesized CPU extensions during runtime; for compatibility: write accesses (in m-mode) are ignored and do not cause an exception
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* `misa` CSR is read-only - no dynamic enabling/disabling of synthesized CPU extensions during runtime; for compatibility: write accesses (in m-mode) are ignored and do not cause an exception
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* The physical memory protection (**PMP**) only supports `NAPOT` mode yet and a minimal granularity of 8 bytes
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* The physical memory protection (**PMP**) only supports `NAPOT` mode yet and a minimal granularity of 8 bytes
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* The `A` extension only implements `lr.w` and `sc.w` instructions yet. However, these instructions are sufficient to emulate all further AMO operations
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* The `A` extension only implements `lr.w` and `sc.w` instructions yet. However, these instructions are sufficient to emulate all further AMO operations
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* The `mcause` trap code `0x80000000` (originally reserved in the RISC-V specs) is used to indicate a hardware reset (as "non-maskable interrupt")
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* The `mcause` trap code `0x80000000` (originally reserved in the RISC-V specs) is used to indicate a hardware reset (as "non-maskable interrupt")
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* The bit manipulation extension is not yet officially ratified, but is expected to stay unchanged. There is no software support in the upstream GCC RISC-V port yet. However, an intrinsic library is provided to utilize the provided bit manipulation extension from C-language code (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation)). NEORV32's `B` extension is compatible to spec. version "0.94-draft".
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## FPGA Implementation Results
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## FPGA Implementation Results
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| Line 296... |
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a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 20.1** ("balanced implementation"). The timing
|
a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 20.1** ("balanced implementation"). The timing
|
information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
|
information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
|
of the CPU's generics is assumed (e.g. no physical memory protection, no hardware performance monitors).
|
of the CPU's generics is assumed (e.g. no physical memory protection, no hardware performance monitors).
|
No constraints were used at all.
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No constraints were used at all.
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|
|
Results generated for hardware version [`1.5.1.4`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
Results generated for hardware version [`1.5.3.2`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
|
|
| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max |
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| CPU Configuration | LEs | FFs | Memory bits | DSPs (9-bit) | f_max |
|
|:-----------------------------------------|:----------:|:--------:|:-----------:|:----:|:-------:|
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|:--------------------------------------------------|:----:|:----:|:-----------:|:------------:|:-------:|
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| `rv32i` | 979 | 409 | 1024 | 0 | 123 MHz |
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| `rv32i` | 980 | 409 | 1024 | 0 | 123 MHz |
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| `rv32i` + `Zicsr` | 1789 | 847 | 1024 | 0 | 122 MHz |
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| `rv32i` + `Zicsr` | 1835 | 856 | 1024 | 0 | 124 MHz |
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| `rv32im` + `Zicsr` | 2381 | 1125 | 1024 | 0 | 122 MHz |
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| `rv32im` + `Zicsr` | 2443 | 1134 | 1024 | 0 | 124 MHz |
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| `rv32imc` + `Zicsr` | 2608 | 1140 | 1024 | 0 | 122 MHz |
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| `rv32imc` + `Zicsr` | 2669 | 1149 | 1024 | 0 | 125 MHz |
|
| `rv32imac` + `Zicsr` | 2621 | 1144 | 1024 | 0 | 122 MHz |
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| `rv32imac` + `Zicsr` | 2685 | 1156 | 1024 | 0 | 124 MHz |
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| `rv32imacb` + `Zicsr` | 3013 | 1310 | 1024 | 0 | 122 MHz |
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| `rv32imac` + `Zicsr` + `u` | 2698 | 1162 | 1024 | 0 | 124 MHz |
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| `rv32imacb` + `Zicsr` + `u` | 3031 | 1313 | 1024 | 0 | 122 MHz |
|
| `rv32imac` + `Zicsr` + `u` + `Zifencei` | 2715 | 1162 | 1024 | 0 | 122 MHz |
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| `rv32imacb` + `Zicsr` + `u` + `Zifencei` | 3050 | 1313 | 1024 | 0 | 116 MHz |
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| `rv32imac` + `Zicsr` + `u` + `Zifencei` + `Zfinx` | 4004 | 1812 | 1024 | 0 | 121 MHz |
|
|
|
Setups with enabled "embedded CPU extension" `E` show the same LUT and FF utilization and identical f_max as the according `I` configuration.
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Setups with enabled "embedded CPU extension" `E` show the same LUT and FF utilization and identical f_max as the according `I` configuration.
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However, the size of the register file is cut in half.
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However, the size of the register file is cut in half.
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|
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|
|
### NEORV32 Processor-Internal Peripherals and Memories
|
### NEORV32 Processor-Internal Peripherals and Memories
|
|
|
Results generated for hardware version [`1.5.2.4`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
Results generated for hardware version [`1.5.3.2`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
|
|
| Module | Description | LEs | FFs | Memory bits | DSPs |
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| Module | Description | LEs | FFs | Memory bits | DSPs (9-bit) |
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|:----------|:-----------------------------------------------------|----:|----:|------------:|-----:|
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|:----------|:-----------------------------------------------------|----:|----:|------------:|-------------:|
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| BOOT ROM | Bootloader ROM (default 4kB) | 3 | 1 | 32 768 | 0 |
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| BOOT ROM | Bootloader ROM (default 4kB) | 3 | 1 | 32 768 | 0 |
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| BUSSWITCH | Bus mux for CPU instr. & data interfaces | 65 | 8 | 0 | 0 |
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| BUSSWITCH | Bus mux for CPU instr. & data interfaces | 65 | 8 | 0 | 0 |
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| i-CACHE | Proc.-int. nstruction cache (default 1x4x64 bytes) | 234 | 156 | 8 192 | 0 |
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| i-CACHE | Proc.-int. nstruction cache (default 1x4x64 bytes) | 234 | 156 | 8 192 | 0 |
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| CFS | Custom functions subsystem | - | - | - | - |
|
| CFS | Custom functions subsystem | - | - | - | - |
|
| DMEM | Processor-internal data memory (default 8kB) | 6 | 2 | 65 536 | 0 |
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| DMEM | Processor-internal data memory (default 8kB) | 6 | 2 | 65 536 | 0 |
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| Line 348... |
Line 352... |
processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals
|
processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals
|
to FPGA pins - except for the Wishbone bus and the interrupt signals. The "default" strategy of each toolchain is used.
|
to FPGA pins - except for the Wishbone bus and the interrupt signals. The "default" strategy of each toolchain is used.
|
|
|
Results generated for hardware version [`1.4.9.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
Results generated for hardware version [`1.4.9.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
|
|
| Vendor | FPGA | Board | Toolchain | CPU Configuration | LUT / LE | FF / REG | DSP | Memory Bits | BRAM / EBR | SPRAM | Frequency |
|
| Vendor | FPGA | Board | Toolchain | CPU Configuration | LUT / LE | FF / REG | DSP (9-bit) | Memory Bits | BRAM / EBR | SPRAM | Frequency |
|
|:--------|:----------------------------------|:-----------------|:---------------------------|:-----------------------------------------------|:-----------|:-----------|:-------|:-------------|:-----------|:---------|--------------:|
|
|:--------|:----------------------------------|:-----------------|:---------------------------|:-----------------------------------------------|:-----------|:-----------|:------------|:-------------|:-----------|:---------|--------------:|
|
| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 20.1 | `rv32imc` + `u` + `Zicsr` + `Zifencei` | 3813 (17%) | 1904 (8%) | 0 (0%) | 231424 (38%) | - | - | 119 MHz |
|
| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 20.1 | `rv32imc` + `u` + `Zicsr` + `Zifencei` | 3813 (17%) | 1904 (8%) | 0 (0%) | 231424 (38%) | - | - | 119 MHz |
|
| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (Synplify Pro) | `rv32ic` + `u` + `Zicsr` + `Zifencei` | 4397 (83%) | 1679 (31%) | 0 (0%) | - | 12 (40%) | 4 (100%) | *c* 22.15 MHz |
|
| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (Synplify Pro) | `rv32ic` + `u` + `Zicsr` + `Zifencei` | 4397 (83%) | 1679 (31%) | 0 (0%) | - | 12 (40%) | 4 (100%) | *c* 22.15 MHz |
|
| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | `rv32imc` + `u` + `Zicsr` + `Zifencei` + `PMP` | 2465 (12%) | 1912 (5%) | 0 (0%) | - | 8 (16%) | - | *c* 100 MHz |
|
| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | `rv32imc` + `u` + `Zicsr` + `Zifencei` + `PMP` | 2465 (12%) | 1912 (5%) | 0 (0%) | - | 8 (16%) | - | *c* 100 MHz |
|
|
|
**_Notes_**
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**_Notes_**
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| Line 547... |
Line 551... |
|
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### 4. Compile an Example Program
|
### 4. Compile an Example Program
|
|
|
The NEORV32 project includes several [example program project](https://github.com/stnolting/neorv32/tree/master/sw/example) from
|
The NEORV32 project includes several [example program project](https://github.com/stnolting/neorv32/tree/master/sw/example) from
|
which you can start your own application. There are example programs to check out the processor's peripheral like I2C or the true-random number generator.
|
which you can start your own application. There are example programs to check out the processor's peripheral like I2C or the true-random number generator.
|
And yes, there is also a port of [Conway's Game of Life](https://github.com/stnolting/neorv32/tree/master/sw/example/game_of_life) available! :wink:
|
And of course there is also a port of [Conway's Game of Life](https://github.com/stnolting/neorv32/tree/master/sw/example/game_of_life) available.
|
|
|
Simply compile one of these projects using
|
Simply compile one of these projects using
|
|
|
neorv32/sw/example/blink_led$ make clean_all exe
|
neorv32/sw/example/blink_led$ make clean_all exe
|
|
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| Line 573... |
Line 577... |
Use the bootloader console to upload the `neorv32_exe.bin` executable gerated during application compiling and *run* your application.
|
Use the bootloader console to upload the `neorv32_exe.bin` executable gerated during application compiling and *run* your application.
|
|
|
```
|
```
|
<< NEORV32 Bootloader >>
|
<< NEORV32 Bootloader >>
|
|
|
BLDV: Nov 7 2020
|
BLDV: Mar 23 2021
|
HWV: 0x01040606
|
HWV: 0x01050208
|
CLK: 0x0134FD90 Hz
|
CLK: 0x05F5E100
|
USER: 0x0001CE40
|
USER: 0x10000DE0
|
MISA: 0x42801104
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MISA: 0x40901105
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PROC: 0x03FF0035
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ZEXT: 0x00000023
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IMEM: 0x00010000 bytes @ 0x00000000
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PROC: 0x0EFF0037
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DMEM: 0x00010000 bytes @ 0x80000000
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IMEM: 0x00004000 bytes @ 0x00000000
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DMEM: 0x00002000 bytes @ 0x80000000
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Autoboot in 8s. Press key to abort.
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Autoboot in 8s. Press key to abort.
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Aborted.
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Aborted.
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Available CMDs:
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Available CMDs:
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