| Line 22... |
Line 22... |
## Overview
|
## Overview
|
|
|
|
|
|
|
The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based
|
The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based
|
on the RISC-V NEORV32 CPU. The processor is intended as auxiliary processor within a larger SoC
|
on the RISC-V NEORV32 CPU. The processor is intended as auxiliary processor in larger SoC
|
designs or as *ready-to-go* stand-alone custom microcontroller.
|
designs or as *ready-to-go* stand-alone custom microcontroller.
|
|
|
:books: For detailed information take a look at the [NEORV32 data sheet (pdf)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
:books: For detailed information take a look at the [NEORV32 data sheet (pdf)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
The doxygen-based documentation of the *software framework* is available online at [GitHub-pages](https://stnolting.github.io/neorv32/files.html).
|
The doxygen-based documentation of the *software framework* is available online at [GitHub-pages](https://stnolting.github.io/neorv32/files.html).
|
|
|
:label: The project’s change log is available as [CHANGELOG.md](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) in the root directory of this repository.
|
:label: The project’s change log is available as [CHANGELOG.md](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) in the root directory of this repository.
|
To see the changes between *stable* releases visit the project's [release page](https://github.com/stnolting/neorv32/releases).
|
To see the changes between *stable* releases visit the project's [release page](https://github.com/stnolting/neorv32/releases).
|
|
|
|
:rocket: The [`boards`](https://github.com/stnolting/neorv32/tree/master/boards) folder provides exemplary setups targeting various FPGA boards to get you started.
|
|
|
:spiral_notepad: Check out the [project boards](https://github.com/stnolting/neorv32/projects) for a list of current **ideas**,
|
:spiral_notepad: Check out the [project boards](https://github.com/stnolting/neorv32/projects) for a list of current **ideas**,
|
**TODOs**, features being **planned** and **work-in-progress**.
|
**TODOs**, features being **planned** and **work-in-progress**.
|
|
|
:bulb: Feel free to open a [new issue](https://github.com/stnolting/neorv32/issues) or start a [new discussion](https://github.com/stnolting/neorv32/discussions)
|
:bulb: Feel free to open a [new issue](https://github.com/stnolting/neorv32/issues) or start a [new discussion](https://github.com/stnolting/neorv32/discussions)
|
if you have questions, comments, ideas or bug-fixes. Check out how to [contribute](#ContributeFeedbackQuestions).
|
if you have questions, comments, ideas or bug-fixes. Check out how to [contribute](#ContributeFeedbackQuestions).
|
| Line 55... |
Line 57... |
* [`M`](#M---Integer-multiplication-and-division-hardware-extension) - integer multiplication and division hardware (optional)
|
* [`M`](#M---Integer-multiplication-and-division-hardware-extension) - integer multiplication and division hardware (optional)
|
* [`U`](#U---Privileged-architecture---User-mode-extension) - less-privileged *user mode* (optional)
|
* [`U`](#U---Privileged-architecture---User-mode-extension) - less-privileged *user mode* (optional)
|
* [`X`](#X---NEORV32-specific-CPU-extensions) - NEORV32-specific extensions (always enabled)
|
* [`X`](#X---NEORV32-specific-CPU-extensions) - NEORV32-specific extensions (always enabled)
|
* [`Zfinx`](#Zfinx---Single-precision-floating-point-extension) - Single-precision floating-point extensions (optional)
|
* [`Zfinx`](#Zfinx---Single-precision-floating-point-extension) - Single-precision floating-point extensions (optional)
|
* [`Zicsr`](#Zicsr---Privileged-architecture---CSR-access-extension) - control and status register access instructions (+ exception/irq system) (optional)
|
* [`Zicsr`](#Zicsr---Privileged-architecture---CSR-access-extension) - control and status register access instructions (+ exception/irq system) (optional)
|
* [`Zifencei`](#Zifencei---Privileged-architecture---Instruction-stream-synchronization-extension) - instruction stream synchronization (optional)
|
* [`Zifencei`](#Zifencei---Instruction-stream-synchronization-extension) - instruction stream synchronization (optional)
|
* [`PMP`](#PMP---Privileged-architecture---Physical-memory-protection) - physical memory protection (optional)
|
* [`PMP`](#PMP---Privileged-architecture---Physical-memory-protection) - physical memory protection (optional)
|
* [`HPM`](#HPM---Privileged-architecture---Hardware-performance-monitors) - hardware performance monitors (optional)
|
* [`HPM`](#HPM---Privileged-architecture---Hardware-performance-monitors) - hardware performance monitors (optional)
|
* Full-scale RISC-V microcontroller system / **SoC** [**NEORV32 Processor**](#NEORV32-Processor-Features) with optional submodules
|
* Full-scale RISC-V microcontroller system / **SoC** [**NEORV32 Processor**](#NEORV32-Processor-Features) with optional submodules
|
* optional embedded memories (instructions/data/bootloader, RAM/ROM) and caches
|
* optional embedded memories (instructions/data/bootloader, RAM/ROM) and caches
|
* timers (watch dog, RISC-V-compatible machine timer)
|
* timers (watch dog, RISC-V-compatible machine timer)
|
| Line 138... |
Line 140... |
* custom functions subsystem (**CFS**) for tightly-coupled custom co-processor extensions
|
* custom functions subsystem (**CFS**) for tightly-coupled custom co-processor extensions
|
* numerically-controlled oscillator (**NCO**) with three independent channels
|
* numerically-controlled oscillator (**NCO**) with three independent channels
|
* smart LED interface (**NEOLED**) - WS2812 / NeoPixel(c) compatible
|
* smart LED interface (**NEOLED**) - WS2812 / NeoPixel(c) compatible
|
* system configuration information memory to check hardware configuration by software (**SYSINFO**)
|
* system configuration information memory to check hardware configuration by software (**SYSINFO**)
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
### NEORV32 CPU Features
|
### NEORV32 CPU Features
|
|
|
The NEORV32 CPU implements the
|
The NEORV32 CPU implements the
|
[official RISC-V specifications (2.2)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the
|
[official RISC-V specifications (2.2)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the
|
| Line 161... |
Line 165... |
* BIG-ENDIAN byte-order, processor's external memory interface allows endianness configuration to connect to system with different endianness
|
* BIG-ENDIAN byte-order, processor's external memory interface allows endianness configuration to connect to system with different endianness
|
* All reserved or unimplemented instructions will raise an illegal instruction exception
|
* All reserved or unimplemented instructions will raise an illegal instruction exception
|
* Privilege levels: `machine` mode, `user` mode (if enabled via `U` extension)
|
* Privilege levels: `machine` mode, `user` mode (if enabled via `U` extension)
|
* Official [RISC-V open-source architecture ID](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md)
|
* Official [RISC-V open-source architecture ID](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md)
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
#### `A` - Atomic memory access extension
|
#### `A` - Atomic memory access extension
|
|
|
* Supported instructions: `LR.W` (load-reservate) `SC.W` (store-conditional)
|
* Supported instructions: `LR.W` (load-reservate) `SC.W` (store-conditional)
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
#### `B` - Bit manipulation instructions extension
|
#### `B` - Bit manipulation instructions extension
|
|
|
* :construction: **work-in-progress** :construction:
|
* :construction: **work-in-progress** :construction:
|
* :warning: this extension has not been officially ratified yet!
|
* :warning: this extension has not been officially ratified yet!
|
| Line 178... |
Line 186... |
* Software support via intrinsic library (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation))
|
* Software support via intrinsic library (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation))
|
* `Zbb` base instruction set: `CLZ` `CTZ` `CPOP` `SEXT.B` `SEXT.H` `MIN[U]` `MAX[U]` `ANDN` `ORN` `XNOR` `ROL` `ROR[I]` `zext`(*pseudo-instruction* for `PACK rd, rs, zero`) `rev8`(*pseudo-instruction* for `GREVI rd, rs, -8`) `orc.b`(*pseudo-instruction* for `GORCI rd, rs, 7`)
|
* `Zbb` base instruction set: `CLZ` `CTZ` `CPOP` `SEXT.B` `SEXT.H` `MIN[U]` `MAX[U]` `ANDN` `ORN` `XNOR` `ROL` `ROR[I]` `zext`(*pseudo-instruction* for `PACK rd, rs, zero`) `rev8`(*pseudo-instruction* for `GREVI rd, rs, -8`) `orc.b`(*pseudo-instruction* for `GORCI rd, rs, 7`)
|
* `Zbs` single-bit instructions: `SBSET[I]` `SBCLR[I]` `SBINV[I]` `SBEXT[I]`
|
* `Zbs` single-bit instructions: `SBSET[I]` `SBCLR[I]` `SBINV[I]` `SBEXT[I]`
|
* `Zba` shifted-add instructions: `SH1ADD` `SH2ADD` `SH3ADD`
|
* `Zba` shifted-add instructions: `SH1ADD` `SH2ADD` `SH3ADD`
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
#### `C` - Compressed instructions extension
|
#### `C` - Compressed instructions extension
|
|
|
* ALU instructions: `C.ADDI4SPN` `C.ADD[I]` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP`
|
* ALU instructions: `C.ADDI4SPN` `C.ADD[I]` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP`
|
* Jump and branch instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ`
|
* Jump and branch instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ`
|
* Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP`
|
* Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP`
|
* System instructions: `C.EBREAK` (requires `Zicsr` extension)
|
* System instructions: `C.EBREAK` (requires `Zicsr` extension)
|
* Pseudo-instructions are not listed
|
* Pseudo-instructions are not listed
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
#### `E` - Embedded CPU version extension
|
#### `E` - Embedded CPU version extension
|
|
|
* Reduced register file (only the 16 lowest registers are implemented)
|
* Reduced register file (only the 16 lowest registers are implemented)
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
#### `I` - Base integer instruction set
|
#### `I` - Base integer instruction set
|
|
|
* ALU instructions: `LUI` `AUIPC` `ADD[I]` `SLT[I][U]` `XOR[I]` `OR[I]` `AND[I]` `SLL[I]` `SRL[I]` `SRA[I]` `SUB`
|
* ALU instructions: `LUI` `AUIPC` `ADD[I]` `SLT[I][U]` `XOR[I]` `OR[I]` `AND[I]` `SLL[I]` `SRL[I]` `SRA[I]` `SUB`
|
* Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
|
* Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
|
* Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW`
|
* Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW`
|
* System instructions: `ECALL` `EBREAK` `FENCE`
|
* System instructions: `ECALL` `EBREAK` `FENCE`
|
* Pseudo-instructions are not listed
|
* Pseudo-instructions are not listed
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
#### `M` - Integer multiplication and division hardware extension
|
#### `M` - Integer multiplication and division hardware extension
|
|
|
* Multiplication instructions: `MUL` `MULH` `MULHSU` `MULHU`
|
* Multiplication instructions: `MUL` `MULH` `MULHSU` `MULHU`
|
* Division instructions: `DIV` `DIVU` `REM` `REMU`
|
* Division instructions: `DIV` `DIVU` `REM` `REMU`
|
* By default, the multiplier and divider cores use an iterative bit-serial processing scheme
|
* By default, the multiplier and divider cores use an iterative bit-serial processing scheme
|
* Multiplications can be mapped to DSPs via the `FAST_MUL_EN` generic to increase performance
|
* Multiplications can be mapped to DSPs via the `FAST_MUL_EN` generic to increase performance
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
#### `U` - Privileged architecture - User mode extension
|
#### `U` - Privileged architecture - User mode extension
|
|
|
* Requires `Zicsr` extension
|
* Requires `Zicsr` extension
|
* Privilege levels: `M` (machine mode) + less-privileged `U` (user mode)
|
* Privilege levels: `M` (machine mode) + less-privileged `U` (user mode)
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
#### `X` - NEORV32-specific CPU extensions
|
#### `X` - NEORV32-specific CPU extensions
|
|
|
* The NEORV32-specific extensions are always enabled and are indicated via the `X` bit set in the `misa` CSR.
|
* The NEORV32-specific extensions are always enabled and are indicated via the `X` bit set in the `misa` CSR.
|
* 16 *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause`
|
* 16 *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause`
|
* `mzext` CSR to check for implemented `Z*` CPU extensions (like `Zifencei`)
|
* `mzext` CSR to check for implemented `Z*` CPU extensions (like `Zifencei`)
|
* All undefined/umimplemented/malformed/illegal instructions do raise an illegal instruction exception
|
* All undefined/umimplemented/malformed/illegal instructions do raise an illegal instruction exception
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
#### `Zfinx` - Single-precision floating-point extension
|
#### `Zfinx` - Single-precision floating-point extension
|
|
|
* :warning: this extension has not been officially ratified yet!
|
* :warning: this extension has not been officially ratified yet!
|
* :books: more information can be found here: [RISC-V `Zfinx` spec.](https://github.com/riscv/riscv-zfinx)
|
* :books: more information can be found here: [RISC-V `Zfinx` spec.](https://github.com/riscv/riscv-zfinx)
|
| Line 234... |
Line 257... |
* Computational instructions: `FADD.S` `FSUB.S` `FMUL.S` `FSGNJ[N/X].S` `FCLASS.S` ~~`FDIV.S`~~ ~~`FSQRT.S`~~
|
* Computational instructions: `FADD.S` `FSUB.S` `FMUL.S` `FSGNJ[N/X].S` `FCLASS.S` ~~`FDIV.S`~~ ~~`FSQRT.S`~~
|
* Comparison instructions: `FMIN.S` `FMAX.S` `FEQ.S` `FLT.S` `FLE.S`
|
* Comparison instructions: `FMIN.S` `FMAX.S` `FEQ.S` `FLT.S` `FLE.S`
|
* Conversion instructions: `FCVT.W.S` `FCVT.WU.S` `FCVT.S.W` `FCVT.S.WU`
|
* Conversion instructions: `FCVT.W.S` `FCVT.WU.S` `FCVT.S.W` `FCVT.S.WU`
|
* Additional CSRs: `fcsr` `frm` `fflags`
|
* Additional CSRs: `fcsr` `frm` `fflags`
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
#### `Zicsr` - Privileged architecture - CSR access extension
|
#### `Zicsr` - Privileged architecture - CSR access extension
|
|
|
* Privilege levels: `M-mode` (Machine mode)
|
* Privilege levels: `M-mode` (Machine mode)
|
* CSR access instructions: `CSRRW[I]` `CSRRS[I]` `CSRRC[I]`
|
* CSR access instructions: `CSRRW[I]` `CSRRS[I]` `CSRRC[I]`
|
| Line 260... |
Line 285... |
* RISC-V machine timer interrupt `mti` (via processor-internal MTIME unit *or* external signal)
|
* RISC-V machine timer interrupt `mti` (via processor-internal MTIME unit *or* external signal)
|
* RISC-V machine software interrupt `msi` (via external signal)
|
* RISC-V machine software interrupt `msi` (via external signal)
|
* RISC-V machine external interrupt `mei` (via external signal)
|
* RISC-V machine external interrupt `mei` (via external signal)
|
* 16 fast interrupt requests, 6+1 available for custom usage
|
* 16 fast interrupt requests, 6+1 available for custom usage
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
#### `Zifencei` - Privileged architecture - Instruction stream synchronization extension
|
#### `Zifencei` - Instruction stream synchronization extension
|
|
|
* System instructions: `FENCE.I` (among others, used to clear and reload instruction cache)
|
* System instructions: `FENCE.I` (among others, used to clear and reload instruction cache)
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
#### `PMP` - Privileged architecture - Physical memory protection
|
#### `PMP` - Privileged architecture - Physical memory protection
|
|
|
* Requires `Zicsr` extension
|
* Requires `Zicsr` extension
|
* Configurable number of regions (0..63)
|
* Configurable number of regions (0..63)
|
* Additional machine CSRs: `pmpcfg*`(0..15) `pmpaddr*`(0..63)
|
* Additional machine CSRs: `pmpcfg*`(0..15) `pmpaddr*`(0..63)
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
#### `HPM` - Privileged architecture - Hardware performance monitors
|
#### `HPM` - Privileged architecture - Hardware performance monitors
|
|
|
* Requires `Zicsr` extension
|
* Requires `Zicsr` extension
|
* Configurable number of counters (0..29)
|
* Configurable number of counters (0..29)
|
* Additional machine CSRs: `mhpmevent*`(3..31) `[m]hpmcounter*[h]`(3..31)
|
* Additional machine CSRs: `mhpmevent*`(3..31) `[m]hpmcounter*[h]`(3..31)
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
### :warning: Non-RISC-V-Compatible Issues and Limitations
|
### :warning: Non-RISC-V-Compatible Issues and Limitations
|
|
|
* CPU and Processor are BIG-ENDIAN, but this should be no problem as the external memory bus interface provides big- and little-endian configurations
|
* CPU and Processor are BIG-ENDIAN, but this should be no problem as the external memory bus interface provides big- and little-endian configurations
|
* `misa` CSR is read-only - no dynamic enabling/disabling of synthesized CPU extensions during runtime; for compatibility: write accesses (in m-mode) are ignored and do not cause an exception
|
* `misa` CSR is read-only - no dynamic enabling/disabling of synthesized CPU extensions during runtime; for compatibility: write accesses (in m-mode) are ignored and do not cause an exception
|
* The physical memory protection (**PMP**) only supports `NAPOT` mode yet and a minimal granularity of 8 bytes
|
* The physical memory protection (**PMP**) only supports `NAPOT` mode yet and a minimal granularity of 8 bytes
|
* The `A` extension only implements `lr.w` and `sc.w` instructions yet. However, these instructions are sufficient to emulate all further AMO operations
|
* The `A` extension only implements `lr.w` and `sc.w` instructions yet. However, these instructions are sufficient to emulate all remaining AMO operations
|
* The `mcause` trap code `0x80000000` (originally reserved in the RISC-V specs) is used to indicate a hardware reset (as "non-maskable interrupt")
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
|
## FPGA Implementation Results
|
## FPGA Implementation Results
|
|
|
| Line 311... |
Line 345... |
| `rv32im` + `Zicsr` | 2443 | 1134 | 1024 | 0 | 124 MHz |
|
| `rv32im` + `Zicsr` | 2443 | 1134 | 1024 | 0 | 124 MHz |
|
| `rv32imc` + `Zicsr` | 2669 | 1149 | 1024 | 0 | 125 MHz |
|
| `rv32imc` + `Zicsr` | 2669 | 1149 | 1024 | 0 | 125 MHz |
|
| `rv32imac` + `Zicsr` | 2685 | 1156 | 1024 | 0 | 124 MHz |
|
| `rv32imac` + `Zicsr` | 2685 | 1156 | 1024 | 0 | 124 MHz |
|
| `rv32imac` + `Zicsr` + `u` | 2698 | 1162 | 1024 | 0 | 124 MHz |
|
| `rv32imac` + `Zicsr` + `u` | 2698 | 1162 | 1024 | 0 | 124 MHz |
|
| `rv32imac` + `Zicsr` + `u` + `Zifencei` | 2715 | 1162 | 1024 | 0 | 122 MHz |
|
| `rv32imac` + `Zicsr` + `u` + `Zifencei` | 2715 | 1162 | 1024 | 0 | 122 MHz |
|
| `rv32imac` + `Zicsr` + `u` + `Zifencei` + `Zfinx` | 4004 | 1812 | 1024 | 0 | 121 MHz |
|
| `rv32imac` + `Zicsr` + `u` + `Zifencei` + `Zfinx` | 4004 | 1812 | 1024 | 7 | 121 MHz |
|
|
|
Setups with enabled "embedded CPU extension" `E` show the same LUT and FF utilization and identical f_max as the according `I` configuration.
|
Setups with enabled "embedded CPU extension" `E` show the same LUT and FF utilization and identical f_max as the according `I` configuration.
|
However, the size of the register file is cut in half.
|
However, the size of the register file is cut in half.
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
### NEORV32 Processor-Internal Peripherals and Memories
|
### NEORV32 Processor-Internal Peripherals and Memories
|
|
|
Results generated for hardware version [`1.5.3.2`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
Results generated for hardware version [`1.5.3.2`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
|
|
| Line 342... |
Line 378... |
| TWI | Two-wire interface | 77 | 46 | 0 | 0 |
|
| TWI | Two-wire interface | 77 | 46 | 0 | 0 |
|
| UART0/1 | Universal asynchronous receiver/transmitter 0/1 | 176 | 132 | 0 | 0 |
|
| UART0/1 | Universal asynchronous receiver/transmitter 0/1 | 176 | 132 | 0 | 0 |
|
| WDT | Watchdog timer | 60 | 45 | 0 | 0 |
|
| WDT | Watchdog timer | 60 | 45 | 0 | 0 |
|
| WISHBONE | External memory interface | 129 | 104 | 0 | 0 |
|
| WISHBONE | External memory interface | 129 | 104 | 0 | 0 |
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
### NEORV32 Processor - Exemplary FPGA Setups
|
### NEORV32 Processor - Exemplary FPGA Setups
|
|
|
Exemplary processor implementation results for different FPGA platforms. The processor setup uses *the default peripheral configuration* (like no _CFS_ and no _TRNG_),
|
:information_source: Check out the [`boards`](https://github.com/stnolting/neorv32/tree/master/boards) folder for exemplary setups targeting various FPGA boards.
|
no external memory interface and only internal instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup's top entity connects most of the
|
|
processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals
|
The following tables show exemplary processor implementation results for different FPGA platforms. The processor setups use *the default peripheral configuration* (like no *CFS* and no *TRNG*),
|
to FPGA pins - except for the Wishbone bus and the interrupt signals. The "default" strategy of each toolchain is used.
|
no external memory interface and only internal instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space.
|
|
|
Results generated for hardware version [`1.4.9.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
Results generated for hardware version [`1.4.9.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
|
|
| Vendor | FPGA | Board | Toolchain | CPU Configuration | LUT / LE | FF / REG | DSP (9-bit) | Memory Bits | BRAM / EBR | SPRAM | Frequency |
|
| Vendor | FPGA | Board | Toolchain | CPU Configuration | LUT / LE | FF / REG | DSP (9-bit) | Memory Bits | BRAM / EBR | SPRAM | Frequency |
|
|:--------|:----------------------------------|:-----------------|:---------------------------|:-----------------------------------------------|:-----------|:-----------|:------------|:-------------|:-----------|:---------|--------------:|
|
|:--------|:----------------------------------|:-----------------|:---------------------------|:-----------------------------------------------|:-----------|:-----------|:------------|:-------------|:-----------|:---------|--------------:|
|
| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 20.1 | `rv32imc` + `u` + `Zicsr` + `Zifencei` | 3813 (17%) | 1904 (8%) | 0 (0%) | 231424 (38%) | - | - | 119 MHz |
|
| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 20.1 | `rv32imc` + `u` + `Zicsr` + `Zifencei` | 3813 (17%) | 1904 (8%) | 0 (0%) | 231424 (38%) | - | - | 119 MHz |
|
| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (Synplify Pro) | `rv32ic` + `u` + `Zicsr` + `Zifencei` | 4397 (83%) | 1679 (31%) | 0 (0%) | - | 12 (40%) | 4 (100%) | *c* 22.15 MHz |
|
| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (Synplify Pro) | `rv32ic` + `u` + `Zicsr` + `Zifencei` | 4397 (83%) | 1679 (31%) | 0 (0%) | - | 12 (40%) | 4 (100%) | *c* 22.15 MHz |
|
| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | `rv32imc` + `u` + `Zicsr` + `Zifencei` + `PMP` | 2465 (12%) | 1912 (5%) | 0 (0%) | - | 8 (16%) | - | *c* 100 MHz |
|
| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | `rv32imc` + `u` + `Zicsr` + `Zifencei` + `PMP` | 2465 (12%) | 1912 (5%) | 0 (0%) | - | 8 (16%) | - | *c* 100 MHz |
|
|
|
**_Notes_**
|
**_Notes_**
|
|
* The "default" implementation strategy of the according toolchain is used.
|
* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DMEM (each 64kb).
|
* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DMEM (each 64kb).
|
The FPGA-specific memory components can be found in [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up).
|
The FPGA-specific memory components can be found in [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up).
|
* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are _f_max_ results from the place and route timing reports.
|
* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are _f_max_ results from the place and route timing reports.
|
* The Upduino and the Arty board have on-board SPI flash memories for storing the FPGA configuration. These device can also be used by the default NEORV32
|
* The Upduino and the Arty board have on-board SPI flash memories for storing the FPGA configuration. These device can also be used by the default NEORV32
|
bootloader to store and automatically boot an application program after reset (both tested successfully).
|
bootloader to store and automatically boot an application program after reset (both tested successfully).
|
* The setups with `PMP` implement 2 regions with a minimal granularity of 64kB.
|
* The setups with `PMP` implement 2 regions with a minimal granularity of 64kB.
|
* No HPM counters are implemented.
|
* No HPM counters are implemented.
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
|
## Performance
|
## Performance
|
|
|
### CoreMark Benchmark
|
### CoreMark Benchmark
|
| Line 379... |
Line 420... |
[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark
|
[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark
|
tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.
|
tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.
|
|
|
~~~
|
~~~
|
**Configuration**
|
**Configuration**
|
Hardware: 32kB IMEM, 16kB DMEM, no caches, 100MHz clock
|
Hardware: 32kB IMEM, 8kB DMEM, no caches, 100MHz clock
|
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
|
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
|
Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain)
|
Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain)
|
Compiler flags: default, see makefile
|
Compiler flags: default, see makefile
|
|
Optimization: -O3
|
Peripherals: UART for printing the results
|
Peripherals: UART for printing the results
|
~~~
|
~~~
|
|
|
Results generated for hardware version [`1.4.9.8`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
Results generated for hardware version [`1.4.9.8`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
|
|
| CPU (including `Zicsr`) | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz |
|
| CPU (including `Zicsr` extension) | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz |
|
|:--------------------------------------------|:---------------:|:------------:|:--------------:|:-------------:|
|
|:--------------------------------------------|:---------------:|:------------:|:--------------:|:-------------:|
|
| `rv32i` | 28 756 bytes | `-O3` | 36.36 | **0.3636** |
|
| `rv32i` | 28 756 bytes | `-O3` | 36.36 | **0.3636** |
|
| `rv32im` | 27 516 bytes | `-O3` | 68.97 | **0.6897** |
|
|
| `rv32imc` | 22 008 bytes | `-O3` | 68.97 | **0.6897** |
|
| `rv32imc` | 22 008 bytes | `-O3` | 68.97 | **0.6897** |
|
| `rv32imc` + `FAST_MUL_EN` | 22 008 bytes | `-O3` | 86.96 | **0.8696** |
|
|
| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` | 22 008 bytes | `-O3` | 90.91 | **0.9091** |
|
| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` | 22 008 bytes | `-O3` | 90.91 | **0.9091** |
|
|
|
The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic). The `FAST_SHIFT_EN` configuration
|
The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic). The `FAST_SHIFT_EN` configuration
|
uses a barrel shifter for CPU shift operations (enabled via the `FAST_SHIFT_EN` generic).
|
uses a barrel shifter for CPU shift operations (enabled via the `FAST_SHIFT_EN` generic).
|
|
|
When the `C` extension is enabled, branches to an unaligned uncompressed instruction require additional instruction fetch cycles.
|
When the `C` extension is enabled, branches to an unaligned uncompressed instruction require additional instruction fetch cycles.
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
### Instruction Cycles
|
### Instruction Cycles
|
|
|
The NEORV32 CPU is based on a two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme. Hence,
|
The NEORV32 CPU is based on a two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme. Hence,
|
each instruction requires several clock cycles to execute (2 cycles for ALU operations, ..., 40 cycles for divisions).
|
each instruction requires several clock cycles to execute (2 cycles for ALU operations, ..., 40 cycles for divisions).
|
| Line 417... |
Line 459... |
dividing the total number of required clock cycles (only the timed core to avoid distortion due to IO wait cycles; sampled via the `cycle[h]` CSRs)
|
dividing the total number of required clock cycles (only the timed core to avoid distortion due to IO wait cycles; sampled via the `cycle[h]` CSRs)
|
by the number of executed instructions (`instret[h]` CSRs). The executables were generated using optimization `-O3`.
|
by the number of executed instructions (`instret[h]` CSRs). The executables were generated using optimization `-O3`.
|
|
|
Results generated for hardware version [`1.4.9.8`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
Results generated for hardware version [`1.4.9.8`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
|
|
| CPU (including `Zicsr`) | Required Clock Cycles | Executed Instructions | Average CPI |
|
| CPU (including `Zicsr` extension) | Required Clock Cycles | Executed Instructions | Average CPI |
|
|:--------------------------------------------|----------------------:|----------------------:|:-----------:|
|
|:--------------------------------------------|----------------------:|----------------------:|:-----------:|
|
| `rv32i` | 5 595 750 503 | 1 466 028 607 | **3.82** |
|
| `rv32i` | 5 595 750 503 | 1 466 028 607 | **3.82** |
|
| `rv32im` | 2 966 086 503 | 598 651 143 | **4.95** |
|
|
| `rv32imc` | 2 981 786 734 | 611 814 918 | **4.87** |
|
| `rv32imc` | 2 981 786 734 | 611 814 918 | **4.87** |
|
| `rv32imc` + `FAST_MUL_EN` | 2 399 234 734 | 611 814 918 | **3.92** |
|
|
| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` | 2 265 135 174 | 611 814 948 | **3.70** |
|
| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` | 2 265 135 174 | 611 814 948 | **3.70** |
|
|
|
The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic). The `FAST_SHIFT_EN` configuration
|
The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic). The `FAST_SHIFT_EN` configuration
|
uses a barrel shifter for CPU shift operations (enabled via the `FAST_SHIFT_EN` generic).
|
uses a barrel shifter for CPU shift operations (enabled via the `FAST_SHIFT_EN` generic).
|
|
|
When the `C` extension is enabled branches to an unaligned uncompressed instruction require additional instruction fetch cycles.
|
When the `C` extension is enabled branches to an unaligned uncompressed instruction require additional instruction fetch cycles.
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
|
## Top Entities
|
## Top Entities
|
|
|
The top entity of the **NEORV32 Processor** (SoC) is [`rtl/core/neorv32_top.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd),
|
The top entity of the **NEORV32 Processor** (SoC) is [`rtl/core/neorv32_top.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd),
|
| Line 452... |
Line 494... |
input ports to zero.
|
input ports to zero.
|
|
|
**Alternative top entities**, like the simplified ["hello world" test setup](#Create-a-new-Hardware-Project) or CPU/Processor
|
**Alternative top entities**, like the simplified ["hello world" test setup](#Create-a-new-Hardware-Project) or CPU/Processor
|
wrappers with resolved port signal types (i.e. *std_logic*), can be found in [`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates).
|
wrappers with resolved port signal types (i.e. *std_logic*), can be found in [`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates).
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
### AXI4 Connectivity
|
### AXI4 Connectivity
|
|
|
Via the [`rtl/top_templates/neorv32_top_axi4lite.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_top_axi4lite.vhd)
|
Via the [`rtl/top_templates/neorv32_top_axi4lite.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_top_axi4lite.vhd)
|
wrapper the NEORV32 provides an **AXI4-Lite** compatible master interface. This wrapper instantiates the default
|
wrapper the NEORV32 provides an **AXI4-Lite** compatible master interface. This wrapper instantiates the default
|
| Line 472... |
Line 516... |
|
|
The setup uses an AXI interconnect to attach two block RAMs to the processor. Since the processor in this example is configured *without* IMEM and DMEM,
|
The setup uses an AXI interconnect to attach two block RAMs to the processor. Since the processor in this example is configured *without* IMEM and DMEM,
|
the attached block RAMs are used for storing instructions and data: the first RAM is used as instruction memory
|
the attached block RAMs are used for storing instructions and data: the first RAM is used as instruction memory
|
and is mapped to address `0x00000000 - 0x00003fff` (16kB), the second RAM is used as data memory and is mapped to address `0x80000000 - 0x80001fff` (8kB).
|
and is mapped to address `0x00000000 - 0x00003fff` (16kB), the second RAM is used as data memory and is mapped to address `0x80000000 - 0x80001fff` (8kB).
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
|
## Getting Started
|
## Getting Started
|
|
|
This overview is just a short excerpt from the *Let's Get It Started* section of the NEORV32 documentary:
|
This overview is just a short excerpt from the *Let's Get It Started* section of the NEORV32 documentary:
|
| Line 518... |
Line 564... |
of this project as [`*.zip` file](https://github.com/stnolting/neorv32/archive/master.zip).
|
of this project as [`*.zip` file](https://github.com/stnolting/neorv32/archive/master.zip).
|
|
|
|
|
### 3. Create a new FPGA Project
|
### 3. Create a new FPGA Project
|
|
|
|
:information_source: If want to use a script-based exemplary project setup check out the [`boards`](https://github.com/stnolting/neorv32/tree/master/boards) folder,
|
|
which provides exemplary setups targeting various FPGA boards.
|
|
|
Create a new project with your FPGA design tool of choice. Add all the `*.vhd` files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl)
|
Create a new project with your FPGA design tool of choice. Add all the `*.vhd` files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl)
|
folder to this project. Make sure to add these files to a **new design library** called `neorv32`.
|
folder to this project. Make sure to add these files to a **new design library** called `neorv32`.
|
|
|
You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) or one of its
|
You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) or one of its
|
[wrappers](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) in your own project. If you just want to try thing out,
|
[wrappers](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) in your own project. If you just want to try thing out,
|
| Line 607... |
Line 656... |
Blinking LED demo program
|
Blinking LED demo program
|
```
|
```
|
|
|
Going further: Take a look at the _Let's Get It Started!_ chapter of the [:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
Going further: Take a look at the _Let's Get It Started!_ chapter of the [:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
## Contribute/Feedback/Questions
|
## Contribute/Feedback/Questions
|
|
|
I'm always thankful for help! So if you have any questions, bug reports, ideas or if you want to give any kind of feedback, feel free
|
I'm always thankful for help! So if you have any questions, bug reports, ideas or if you want to give any kind of feedback, feel free
|
| Line 626... |
Line 676... |
4. Create a new remote for the upstream repo: `git remote add upstream https://github.com/stnolting/neorv32`
|
4. Create a new remote for the upstream repo: `git remote add upstream https://github.com/stnolting/neorv32`
|
5. Commit your modifications: `git commit -m "Awesome new feature!"`
|
5. Commit your modifications: `git commit -m "Awesome new feature!"`
|
6. Push to the branch: `git push origin awesome_new_feature_branch`
|
6. Push to the branch: `git push origin awesome_new_feature_branch`
|
7. Create a new [pull request](https://github.com/stnolting/neorv32/pulls)
|
7. Create a new [pull request](https://github.com/stnolting/neorv32/pulls)
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
## Legal
|
## Legal
|
|
|
This project is released under the BSD 3-Clause license. No copyright infringement intended.
|
This project is released under the BSD 3-Clause license. No copyright infringement intended.
|
Other implied or used projects might have different licensing - see their documentation to get more information.
|
Other implied or used projects might have different licensing - see their documentation to get more information.
|
| Line 688... |
Line 740... |
|
|
"AXI", "AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc.
|
"AXI", "AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc.
|
|
|
"NeoPixel" is a trademark of Adafruit Industries.
|
"NeoPixel" is a trademark of Adafruit Industries.
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
|
## Acknowledgements
|
## Acknowledgements
|
|
|
[](https://riscv.org/)
|
[](https://riscv.org/)
|
| Line 702... |
Line 756... |
|
|
|
|
|
|
This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
|
This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
--------
|
--------
|
|
|
Made with :coffee: in Hannover, Germany :eu:
|
Made with :coffee: in Hannover, Germany :eu:
|
