| Line 54... |
Line 54... |
* The processor has to fit in a Lattice iCE40 UltraPlus 5k FPGA running at 20+ MHz.
|
* The processor has to fit in a Lattice iCE40 UltraPlus 5k FPGA running at 20+ MHz.
|
|
|
|
|
### Status
|
### Status
|
|
|
|
The processor is synthesizable (tested with Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/LSE) and can successfully execute
|
|
all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the CoreMark benchmark.
|
|
|
|
The processor passes the `rv32i`, `rv32im`, `rv32imc` and `rv32Zicsr` *RISC-V compliance tests*.
|
|
|
|
[RISC-V compliance test](https://github.com/stnolting/neorv32_compliance_test):
|
|
[](https://travis-ci.com/stnolting/neorv32_riscv_compliance)
|
|
|
The processor is synthesizable (tested with Intel Quartus Prime and Lattice Radiant/Synplify) and can successfully execute all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example).
|
|
|
|
## Features
|
## Features
|
|
|
|
|
|
|
| Line 71... |
Line 76... |
- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
|
- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
|
- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework
|
- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework
|
- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc.
|
- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc.
|
- Fully synchronous design, no latches, no gated clocks
|
- Fully synchronous design, no latches, no gated clocks
|
- Small hardware footprint and high operating frequency
|
- Small hardware footprint and high operating frequency
|
- Highly customizable processor configuration
|
- Customizable processor configuration
|
- Optional processor-internal data and instruction memories (DMEM/IMEM)
|
- Optional processor-internal data and instruction memories (DMEM/IMEM)
|
- Optional internal bootloader with UART console and automatic SPI flash boot option
|
- Optional internal bootloader with UART console and automatic SPI flash boot option
|
- Optional machine system timer (MTIME), RISC-V-compliant
|
- Optional machine system timer (MTIME), RISC-V-compliant
|
- Optional universal asynchronous receiver and transmitter (UART)
|
- Optional universal asynchronous receiver and transmitter (UART)
|
- Optional 8/16/24/32-bit serial peripheral interface master (SPI) with 8 dedicated chip select lines
|
- Optional 8/16/24/32-bit serial peripheral interface master (SPI) with 8 dedicated chip select lines
|
| Line 133... |
Line 138... |
* Machine software instrrupt
|
* Machine software instrrupt
|
* Machine timer interrupt (via `MTIME` unit)
|
* Machine timer interrupt (via `MTIME` unit)
|
* Machine external interrupt (via `CLIC` unit)
|
* Machine external interrupt (via `CLIC` unit)
|
|
|
**General**:
|
**General**:
|
* No hardware support of unaligned accesses (except for instructions in `C` extension that still have to be aligned on 16-bit boundaries)
|
* No hardware support of unaligned accesses - they will trigger and exception
|
* Multi-cycle in-order instruction execution
|
* Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle execution
|
|
|
More information including a detailed list of the available CSRs can be found in
|
More information including a detailed list of the available CSRs can be found in
|
the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
|
|
|
|
### To-Do / Wish List
|
### To-Do / Wish List
|
|
|
- Testing, testing and even more testing
|
- No exception is triggered in `E`-mode when using reg >x15 yet
|
- Port official [RISC-V compliance test](https://github.com/riscv/riscv-compliance)
|
|
- Port Dhrystone benchmark
|
- Port Dhrystone benchmark
|
- Implement atomic extensions (`A` extension)
|
- Implement atomic operations (`A` extension)
|
- Implement co-processor for single-precision floating-point (`F` extension)
|
- Implement `Zifence` extension
|
|
- Implement co-processor for single-precision floating-point operations (`F` extension)
|
- Implement user mode (`U` extension)
|
- Implement user mode (`U` extension)
|
- Make a 64-bit branch
|
- Make a 64-bit branch
|
- Maybe port an RTOS (like [freeRTOS](https://www.freertos.org/) or [RIOT](https://www.riot-os.org/))
|
- Maybe port an RTOS (like [freeRTOS](https://www.freertos.org/) or [RIOT](https://www.riot-os.org/))
|
|
|
|
|
| Line 160... |
Line 165... |
This chapter shows exemplary implementation results of the NEORV32 processor for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
|
This chapter shows exemplary implementation results of the NEORV32 processor for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
|
a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing
|
a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing
|
information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
|
information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
|
of the processor's generics is assumed. No constraints were used.
|
of the processor's generics is assumed. No constraints were used.
|
|
|
Results generated for hardware version: `0.0.2.3`
|
Results generated for hardware version: `1.0.0.0`
|
|
|
### CPU
|
### CPU
|
|
|
| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max |
|
| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max |
|
|:--------------------|:----------:|:--------:|:-----------:|:------:|:-------:|
|
|:--------------------|:----------:|:--------:|:-----------:|:------:|:-------:|
|
| `rv32i` | 852 (4%) | 326 (1%) | 2048 (>1%) | 0 (0%) | 111 MHz |
|
| `rv32i` | 1027 | 474 | 2048 | 0 (0%) | 111 MHz |
|
| `rv32i` + `Zicsr` | 1488 (7%) | 694 (3%) | 2048 (>1%) | 0 (0%) | 107 MHz |
|
| `rv32i` + `Zicsr` | 1721 | 868 | 2048 | 0 (0%) | 104 MHz |
|
| `rv32im` + `Zicsr` | 2057 (9%) | 941 (4%) | 2048 (>1%) | 0 (0%) | 102 MHz |
|
| `rv32im` + `Zicsr` | 2298 | 1115 | 2048 | 0 (0%) | 103 MHz |
|
| `rv32imc` + `Zicsr` | 2209 (10%) | 958 (4%) | 2048 (>1%) | 0 (0%) | 102 MHz |
|
| `rv32imc` + `Zicsr` | 2557 | 1138 | 2048 | 0 (0%) | 103 MHz |
|
| `rv32e` | 848 (4%) | 326 (1%) | 1024 (>1%) | 0 (0%) | 111 MHz |
|
| `rv32emc` + `Zicsr` | 2342 | 1005 | 1024 | 0 (0%) | 100 MHz |
|
| `rv32e` + `Zicsr` | 1316 (6%) | 594 (3%) | 1024 (>1%) | 0 (0%) | 106 MHz |
|
|
| `rv32em` + `Zicsr` | 1879 (8%) | 841 (4%) | 1024 (>1%) | 0 (0%) | 101 MHz |
|
|
| `rv32emc` + `Zicsr` | 2065 (9%) | 858 (4%) | 1024 (>1%) | 0 (0%) | 100 MHz |
|
|
|
|
### Peripherals / Others
|
### Processor-Internal Peripherals and Memories
|
|
|
| Module | Description | LEs | FFs | Memory bits | DSPs |
|
| Module | Description | LEs | FFs | Memory bits | DSPs |
|
|:---------|:------------------------------------------------|:---:|:---:|:-----------:|:----:|
|
|:---------|:------------------------------------------------|:---:|:---:|:-----------:|:----:|
|
| BOOT ROM | Bootloader ROM (4kB) | 3 | 1 | 32 768 | 0 |
|
| BOOT ROM | Bootloader ROM (4kB) | 3 | 1 | 32 768 | 0 |
|
| DEVNULL | Dummy device | 2 | 1 | 0 | 0 |
|
| DEVNULL | Dummy device | 3 | 1 | 0 | 0 |
|
| DMEM | Processor-internal data memory (8kB) | 12 | 2 | 65 536 | 0 |
|
| DMEM | Processor-internal data memory (8kB) | 12 | 2 | 65 536 | 0 |
|
| GPIO | General purpose input/output ports | 37 | 33 | 0 | 0 |
|
| GPIO | General purpose input/output ports | 38 | 33 | 0 | 0 |
|
| IMEM | Processor-internal instruction memory (16kb) | 7 | 2 | 131 072 | 0 |
|
| IMEM | Processor-internal instruction memory (16kb) | 7 | 2 | 131 072 | 0 |
|
| MTIME | Machine system timer | 369 | 168 | 0 | 0 |
|
| MTIME | Machine system timer | 270 | 167 | 0 | 0 |
|
| PWM | Pulse-width modulation controller | 77 | 69 | 0 | 0 |
|
| PWM | Pulse-width modulation controller | 76 | 69 | 0 | 0 |
|
| SPI | Serial peripheral interface | 198 | 125 | 0 | 0 |
|
| SPI | Serial peripheral interface | 206 | 125 | 0 | 0 |
|
| TRNG | True random number generator | 103 | 93 | 0 | 0 |
|
| TRNG | True random number generator | 104 | 93 | 0 | 0 |
|
| TWI | Two-wire interface | 76 | 44 | 0 | 0 |
|
| TWI | Two-wire interface | 78 | 44 | 0 | 0 |
|
| UART | Universal asynchronous receiver/transmitter | 154 | 108 | 0 | 0 |
|
| UART | Universal asynchronous receiver/transmitter | 151 | 108 | 0 | 0 |
|
| WDT | Watchdog timer | 57 | 45 | 0 | 0 |
|
| WDT | Watchdog timer | 57 | 45 | 0 | 0 |
|
|
|
|
### CPU + Peripheral
|
|
|
|
The following table shows the implementation results for an _Intel Cyclone IV EP4CE22F17C6N_ FPGA.
|
|
The design was synthesized using Intel Quartus Prime Lite 19.1 (“balanced implementation”).
|
|
IMEM uses 16kB and DMEM uses 8kB memory space.
|
|
|
|
| CPU Configuration | LEs | REGs | DSPs | Memory Bits | f_max |
|
|
|:--------------------|:----------:|:---------:|:------:|:------------:|:-------:|
|
|
| `rv32imc` + `Zicsr` | 3724 (17%) | 1899 (9%) | 0 (0%) | 231424 (38%) | 103 MHz |
|
|
|
|
|
### Lattice iCE40 UltraPlus 5k
|
### Lattice iCE40 UltraPlus 5k
|
|
|
The following table shows the hardware utilization for a [iCE40 UP5K](http://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40UltraPlus) FPGA.
|
The following table shows the hardware utilization for a [iCE40 UP5K](http://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40UltraPlus) FPGA.
|
The setup uses all provided peripherals, all CPU extensions (except for the `E` extension), no external memory interface and internal
|
The setup uses all provided peripherals, all CPU extensions (except for the `E` extension), no external memory interface and internal
|
| Line 203... |
Line 215... |
[`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up) folder.
|
[`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up) folder.
|
|
|
Place & route reports generated with **Lattice Radiant 2.1** using Lattice LSE. The clock frequency
|
Place & route reports generated with **Lattice Radiant 2.1** using Lattice LSE. The clock frequency
|
is constrained and generated via the PLL from the internal HF oscillator running at 12 MHz.
|
is constrained and generated via the PLL from the internal HF oscillator running at 12 MHz.
|
|
|
Results generated for hardware version: `0.0.2.5`
|
| CPU Configuration | LUTs | REGs | DSPs | SPRAM | EBR | f |
|
|
|:--------------------|:----------:|:----------:|:------:|:--------:|:--------:|:---------:|
|
| CPU Configuration | Slices | LUT | REG | DSPs | SPRAM | EBR | f |
|
| `rv32imc` + `Zicsr` | 4985 (94%) | 1982 (38%) | 0 (0%) | 4 (100%) | 12 (40%) | 20.25 MHz |
|
|:--------------------|:----------:|:----------:|:----------:|:------:|:--------:|:--------:|:---------:|
|
|
| `rv32imc` + `Zicsr` | 2405 (91%) | 4642 (87%) | 1810 (34%) | 0 (0%) | 4 (100%) | 12 (40%) | 20.25 MHz |
|
|
|
|
|
|
## Performance
|
## Performance
|
|
|
### CoreMark Benchmark
|
### CoreMark Benchmark
|
|
|
The [CoreMark CPU benchmark](https://www.eembc.org/coremark) was executed on the NEORV32 and is available in the
|
The [CoreMark CPU benchmark](https://www.eembc.org/coremark) was executed on the NEORV32 and is available in the
|
[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark
|
[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark
|
tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.
|
tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.
|
|
|
Results generated for hardware version: `0.0.2.3`
|
Results generated for hardware version: `1.0.0.0`
|
|
|
~~~
|
~~~
|
**Configuration**
|
**Configuration**
|
Hardware: 32kB IMEM, 16kb DMEM, 100MHz clock
|
Hardware: 32kB IMEM, 16kb DMEM, 100MHz clock
|
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
|
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
|
| Line 230... |
Line 240... |
Used peripherals: MTIME for time measurement, UART for printing the results
|
Used peripherals: MTIME for time measurement, UART for printing the results
|
~~~
|
~~~
|
|
|
| __Configuration__ | __Optimization__ | __Executable Size__ | __CoreMark Score__ | __CoreMarks/MHz__ |
|
| __Configuration__ | __Optimization__ | __Executable Size__ | __CoreMark Score__ | __CoreMarks/MHz__ |
|
|:------------------|:----------------:|:-------------------:|:------------------:|:-----------------:|
|
|:------------------|:----------------:|:-------------------:|:------------------:|:-----------------:|
|
| `rv32i` | `-Os` | 17 944 bytes | 23.26 | 0.232 |
|
| `rv32i` | `-Os` | 18 044 bytes | 21.98 | 0.21 |
|
| `rv32i` | `-O2` | 20 264 bytes | 25.64 | 0.256 |
|
| `rv32i` | `-O2` | 20 388 bytes | 25 | 0.25 |
|
| `rv32im` | `-Os` | 16 880 bytes | 40.81 | 0.408 |
|
| `rv32im` | `-Os` | 16 980 bytes | 40 | 0.40 |
|
| `rv32im` | `-O2` | 19 312 bytes | 47.62 | 0.476 |
|
| `rv32im` | `-O2` | 19 436 bytes | 51.28 | 0.51 |
|
| `rv32imc` | `-Os` | 13 000 bytes | 32.78 | 0.327 |
|
| `rv32imc` | `-Os` | 13 076 bytes | 39.22 | 0.39 |
|
| `rv32imc` | `-O2` | 15 004 bytes | 37.04 | 0.370 |
|
| `rv32imc` | `-O2` | 15 208 bytes | 50 | 0.50 |
|
|
|
|
|
### Instruction Cycles
|
### Instruction Cycles
|
|
|
The NEORV32 CPU is based on a multi-cycle architecture. Each instruction is executed in a sequence of several
|
The NEORV32 CPU is based on a multi-cycle architecture. Each instruction is executed in a sequence of several
|
| Line 248... |
Line 258... |
CPU extensions.
|
CPU extensions.
|
|
|
Please note that the CPU-internal shifter (e.g. for the `SLL` instruction) as well as the multiplier and divider of the
|
Please note that the CPU-internal shifter (e.g. for the `SLL` instruction) as well as the multiplier and divider of the
|
`M` extension use a bit-serial approach and require several cycles for completion.
|
`M` extension use a bit-serial approach and require several cycles for completion.
|
|
|
The following table shows the performance results for successfully (!) running 2000 CoreMark
|
The following table shows the performance results for successfully running 2000 CoreMark
|
iterations. The average CPI is computed by dividing the total number of required clock cycles (all of CoreMark
|
iterations. The average CPI is computed by dividing the total number of required clock cycles (all of CoreMark
|
– not only the timed core) by the number of executed instructions (`instret[h]` CSRs). The executables
|
– not only the timed core) by the number of executed instructions (`instret[h]` CSRs). The executables
|
were generated using optimization `-O2`.
|
were generated using optimization `-O2`.
|
|
|
| CPU / Toolchain Config. | Required Clock Cycles | Executed Instructions | Average CPI |
|
| CPU / Toolchain Config. | Required Clock Cycles | Executed Instructions | Average CPI |
|
|:------------------------|----------------------:|----------------------:|:-----------:|
|
|:------------------------|----------------------:|----------------------:|:-----------:|
|
| `rv32i` | 10 385 023 697 | 1 949 310 506 | 5.3 |
|
| `rv32i` | 19 355 607 369 | 2 995 064 579 | 6.5 |
|
| `rv32im` | 6 276 943 488 | 995 011 883 | 6.3 |
|
| `rv32im` | 5 809 384 583 | 867 377 291 | 6.7 |
|
| `rv32imc` | 7 340 734 652 | 934 952 588 | 7.6 |
|
| `rv32imc` | 5 560 220 723 | 825 898 407 | 6.7 |
|
|
|
|
|
### Evaluation
|
|
|
|
Based on the provided performance measurement and the hardware utilization for the
|
|
different CPU configurations, the following configurations are suggested:
|
|
|
|
|
|
| Design Goal | NEORV32 CPU Config. |
|
|
|:-------------------------------|:--------------------|
|
|
| Highest performance: | `rv32im` |
|
|
| Lowest memory requirements: | `rv32imc` |
|
|
| Lowest hardware requirements*: | `rv32ec` |
|
|
|
|
*) Including on-chip memory hardware requirements.
|
|
|
|
|
|
|
|
## Top Entity
|
## Top Entity
|
|
|
| Line 292... |
Line 287... |
generic (
|
generic (
|
-- General --
|
-- General --
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
|
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
| Line 345... |
Line 341... |
gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input
|
gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input
|
-- UART (available if IO_UART_USE = true) --
|
-- UART (available if IO_UART_USE = true) --
|
uart_txd_o : out std_ulogic; -- UART send data
|
uart_txd_o : out std_ulogic; -- UART send data
|
uart_rxd_i : in std_ulogic := '0'; -- UART receive data
|
uart_rxd_i : in std_ulogic := '0'; -- UART receive data
|
-- SPI (available if IO_SPI_USE = true) --
|
-- SPI (available if IO_SPI_USE = true) --
|
spi_sclk_o : out std_ulogic; -- serial clock line
|
spi_sck_o : out std_ulogic; -- serial clock line
|
spi_mosi_o : out std_ulogic; -- serial data line out
|
spi_sdo_o : out std_ulogic; -- serial data line out
|
spi_miso_i : in std_ulogic := '0'; -- serial data line in
|
spi_sdi_i : in std_ulogic := '0'; -- serial data line in
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
-- TWI (available if IO_TWI_USE = true) --
|
-- TWI (available if IO_TWI_USE = true) --
|
twi_sda_io : inout std_logic := 'H'; -- twi serial data line
|
twi_sda_io : inout std_logic := 'H'; -- twi serial data line
|
twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
|
twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
|
-- PWM (available if IO_PWM_USE = true) --
|
-- PWM (available if IO_PWM_USE = true) --
|
| Line 410... |
Line 406... |
Now its time to get the most recent version the NEORV32 Processor project from GitHub. Clone the NEORV32 repository using
|
Now its time to get the most recent version the NEORV32 Processor project from GitHub. Clone the NEORV32 repository using
|
`git` from the command line (suggested for easy project updates via `git pull`):
|
`git` from the command line (suggested for easy project updates via `git pull`):
|
|
|
$ git clone https://github.com/stnolting/neorv32.git
|
$ git clone https://github.com/stnolting/neorv32.git
|
|
|
Create a new HW project with your FPGA synthesis tool of choice. Add all files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl)
|
Create a new HW project with your FPGA design tool of choice. Add all files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl)
|
folder to this project and add them to a **new library** called `neorv32`.
|
folder to this project and add them to a **new library** called `neorv32`.
|
|
|
You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32#top-entity) in you own project, or you
|
You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32#top-entity) in you own project, or you
|
can use a simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) as top entity. This test
|
can use a simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) as top entity. This test
|
setup instantiates the processor, implements most of the peripherals and the basic ISA. Only the UART, clock, reset and some GPIO output sginals are
|
setup instantiates the processor, implements most of the peripherals and the basic ISA. Only the UART, clock, reset and some GPIO output sginals are
|
| Line 462... |
Line 458... |
- No transmission / flow control protocol (raw bytes only)
|
- No transmission / flow control protocol (raw bytes only)
|
- Newline on `\r\n` (carriage return & newline)
|
- Newline on `\r\n` (carriage return & newline)
|
|
|
Use the bootloader console to upload and execute your application image.
|
Use the bootloader console to upload and execute your application image.
|
|
|
```
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<< NEORV32 Bootloader >>
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BLDV: Jun 22 2020
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HWV: 0.0.2.3
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CLK: 0x0134FD90 Hz
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MISA: 0x42801104
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CONF: 0x01FF0015
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IMEM: 0x00010000 bytes @ 0x00000000
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DMEM: 0x00010000 bytes @ 0x80000000
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Autoboot in 8s. Press key to abort.
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Aborted.
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Available commands:
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h: Help
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r: Restart
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u: Upload
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s: Store to flash
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l: Load from flash
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e: Execute
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CMD:>
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```
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Going further: Take a look at the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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Going further: Take a look at the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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## Contact
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## Contact
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## Legal
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## Legal
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This is a hobby project released under the BSD 3-Clause license. No copyright infringement intended.
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This is a hobby project released under the BSD 3-Clause license. No copyright infringement intended.
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Other implied/used projects might have different licensing - see their documentation to get more information.
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**BSD 3-Clause License**
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**BSD 3-Clause License**
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Copyright (c) 2020, Stephan Nolting. All rights reserved.
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Copyright (c) 2020, Stephan Nolting. All rights reserved.
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This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
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This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
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Made with :heart: in Hannover, Germany.
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Made with :coffee: in Hannover, Germany.
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Made with :coffee: in Hannover, Germany.
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Made with :coffee: in Hannover, Germany.
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