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# The NEORV32 RISC-V Processor
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# The NEORV32 RISC-V Processor
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[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[](https://github.com/stnolting/neorv32/releases)
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[](https://github.com/stnolting/neorv32/releases)
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[](https://doi.org/10.5281/zenodo.5121427)
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[](https://doi.org/10.5281/zenodo.5018888)
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[](https://github.com/stnolting/neorv32/releases/tag/nightly)
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[](https://github.com/stnolting/neorv32/releases/tag/nightly)
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[](https://stnolting.github.io/neorv32)
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[](https://stnolting.github.io/neorv32)
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[](https://github.com/stnolting/neorv32/releases/tag/nightly)
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[](https://github.com/stnolting/neorv32/releases/tag/nightly)
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[](https://stnolting.github.io/neorv32/ug)
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[](https://stnolting.github.io/neorv32/ug)
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:label: The project's change log is available in [`CHANGELOG.md`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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:label: The project's change log is available in [`CHANGELOG.md`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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To see the changes between *official* releases visit the project's [release page](https://github.com/stnolting/neorv32/releases).
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To see the changes between *official* releases visit the project's [release page](https://github.com/stnolting/neorv32/releases).
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:package: The [`setups`](https://github.com/stnolting/neorv32/tree/master/setups) folder provides exemplary setups targeting
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:package: The [`setups`](https://github.com/stnolting/neorv32/tree/master/setups) folder provides exemplary setups targeting
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various FPGA boards and toolchains to get you started. Several example programs to be run on your setup can be found in
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various FPGA boards and toolchains to get you started. Several example programs (including a FreeRTOS port) to be run on your setup
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[`sw/example`](https://github.com/stnolting/neorv32/tree/master/sw/example).
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can be found in [`sw/example`](https://github.com/stnolting/neorv32/tree/master/sw/example).
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:kite: Upstream [**Zephyr RTOS**](https://docs.zephyrproject.org/latest/boards/riscv/neorv32/doc/index.html) support.
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:spiral_notepad: Check out the [project boards](https://github.com/stnolting/neorv32/projects) for a list of current **ideas**,
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:spiral_notepad: Check out the [project boards](https://github.com/stnolting/neorv32/projects) for a list of current **ideas**,
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**TODOs**, features being **planned** and **work-in-progress**.
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**TODOs**, features being **planned** and **work-in-progress**.
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:bulb: Feel free to open a [new issue](https://github.com/stnolting/neorv32/issues) or start a
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:bulb: Feel free to open a [new issue](https://github.com/stnolting/neorv32/issues) or start a
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### Project Key Features
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### Project Key Features
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- [x] all-in-one: [CPU](#NEORV32-CPU-Features) plus [Processor/SoC](#NEORV32-Processor-Features) plus [Software Framework & Tooling](#Software-Framework-and-Tooling)
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- [x] all-in-one: [CPU](#NEORV32-CPU-Features) plus [Processor/SoC](#NEORV32-Processor-Features) plus [Software Framework & Tooling](#Software-Framework-and-Tooling)
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- [x] completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
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- [x] completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
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- [x] fully synchronous design, no latches, no gated clocks
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- [x] fully synchronous design, no latches, no gated clocks
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- [x] be as small as possible (while being as RISC-V-compliant as possible) – but with a reasonable size-performance trade-off
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- [x] be as small as possible while being as RISC-V-compliant as possible – but with a reasonable size-performance trade-off:
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(the processor has to fit in a Lattice iCE40 UltraPlus 5k low-power FPGA running at 22+ MHz)
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the processor (CPU _including_ privileged architecture) fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz
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- [x] from zero to `printf("hello world!");` - completely open source and documented
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- [x] from zero to `printf("hello world!");` - completely open source and documented
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- [x] easy to use even for FPGA/RISC-V starters – intended to work *out of the box*
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- [x] easy to use even for FPGA/RISC-V starters – intended to work *out of the box*
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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**SoC Connectivity and Integration**
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**SoC Connectivity and Integration**
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* 32-bit external bus interface, Wishbone b4 compatible
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* 32-bit external bus interface, Wishbone b4 compatible
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([WISHBONE](https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite))
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([WISHBONE](https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite))
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* [wrapper](https://github.com/stnolting/neorv32/blob/master/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd) for AXI4-Lite master interface
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* [wrapper](https://github.com/stnolting/neorv32/blob/master/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd) for AXI4-Lite master interface
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* [wrapper](https://github.com/stnolting/neorv32/blob/master/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd) for Avalon-MM master interface
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* 32-bit stream link interface with up to 8 independent RX and TX links
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* 32-bit stream link interface with up to 8 independent RX and TX links
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([SLINK](https://stnolting.github.io/neorv32/#_stream_link_interface_slink))
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([SLINK](https://stnolting.github.io/neorv32/#_stream_link_interface_slink))
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* AXI4-Stream compatible
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* AXI4-Stream compatible
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* external interrupt controller with up to 32 channels
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* external interrupt controller with up to 32 channels
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([XIRQ](https://stnolting.github.io/neorv32/#_external_interrupt_controller_xirq))
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([XIRQ](https://stnolting.github.io/neorv32/#_external_interrupt_controller_xirq))
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* [core libraries](https://github.com/stnolting/neorv32/tree/master/sw/lib) for high-level usage of the provided functions and peripherals
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* [core libraries](https://github.com/stnolting/neorv32/tree/master/sw/lib) for high-level usage of the provided functions and peripherals
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* application compilation based on GNU makefiles
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* application compilation based on GNU makefiles
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* gcc-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv-gcc-prebuilt))
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* gcc-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv-gcc-prebuilt))
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* bootloader with UART interface console
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* bootloader with UART interface console
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* runtime environment for handling traps
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* runtime environment for handling traps
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* several [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) to get started including CoreMark, FreeRTOS and *Conway's Game of Life*
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* several [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) to get started including
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* `doxygen`-based documentation, available on [GitHub pages](https://stnolting.github.io/neorv32/sw/files.html)
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[CoreMark](https://github.com/stnolting/neorv32/tree/master/sw/example/coremark),
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[FreeRTOS](https://github.com/stnolting/neorv32/tree/master/sw/example/demo_freeRTOS) and
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[Conway's Game of Life](https://github.com/stnolting/neorv32/tree/master/sw/example/game_of_life)
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* `doxygen`-based documentation, available on :books: [GitHub pages](https://stnolting.github.io/neorv32/sw/files.html)
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* supports implementation using open source tooling (GHDL, Yosys and nextpnr; in the future Verilog-to-Routing); both, software and hardware can be
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* supports implementation using open source tooling (GHDL, Yosys and nextpnr; in the future Verilog-to-Routing); both, software and hardware can be
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developed and debugged with open source tooling
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developed and debugged with open source tooling
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* continuous Integration is available for:
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* [continuous integration](https://github.com/stnolting/neorv32/actions) :octocat: is available for:
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* allowing users to see the expected execution/output of the tools
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* allowing users to see the expected execution/output of the tools
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* ensuring specification compliance
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* ensuring specification compliance
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* catching regressions
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* catching regressions
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* providing ready-to-use and up-to-date bitstreams and documentation
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* providing ready-to-use and up-to-date bitstreams and documentation
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