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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU.
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU.
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The project is intended as auxiliary processor in larger SoC designs or as *ready-to-go* stand-alone
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The project is intended as auxiliary processor in larger SoC designs or as *ready-to-go* stand-alone
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custom / customizable microcontroller.
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custom / customizable microcontroller.
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Special focus is paid on **execution safety** to provide defined and predictable behavior at any time.
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Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions
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are executed. Whenever an unexpected situation occurs, the application code is informed via hardware exceptions.
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:information_source: Want to know more? Check out the [project's rationale](https://stnolting.github.io/neorv32/#_rationale).
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:information_source: Want to know more? Check out the [project's rationale](https://stnolting.github.io/neorv32/#_rationale).
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:books: For detailed information take a look at the [NEORV32 documentation (online at GitHub-pages)](https://stnolting.github.io/neorv32/).
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:books: For detailed information take a look at the [NEORV32 documentation (online at GitHub-pages)](https://stnolting.github.io/neorv32/).
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The *doxygen*-based documentation of the *software framework* is also available online
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The *doxygen*-based documentation of the *software framework* is also available online
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at [GitHub-pages](https://stnolting.github.io/neorv32/sw/files.html).
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at [GitHub-pages](https://stnolting.github.io/neorv32/sw/files.html).
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* _true random_ number generator ([TRNG](https://stnolting.github.io/neorv32/#_true_random_number_generator_trng))
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* _true random_ number generator ([TRNG](https://stnolting.github.io/neorv32/#_true_random_number_generator_trng))
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* on-chip debugger ([OCD](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd)) via JTGA - implementing
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* on-chip debugger ([OCD](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd)) via JTGA - implementing
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the [*Minimal RISC-V Debug Specification Version 0.13.2*](https://github.com/riscv/riscv-debug-spec)
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the [*Minimal RISC-V Debug Specification Version 0.13.2*](https://github.com/riscv/riscv-debug-spec)
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and compatible with *OpenOCD* and *gdb*
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and compatible with *OpenOCD* and *gdb*
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* bus keeper to monitor processor-internal bus transactions ([BUSKEEPER](https://stnolting.github.io/neorv32/#_internal_bus_monitor_buskeeper))
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:information_source: It is recommended to use the processor setup even if you want to **use the CPU in stand-alone mode**.
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:information_source: It is recommended to use the processor setup even if you want to **use the CPU in stand-alone mode**.
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Just disable all optional processor-internal modules via the according generics and you will get a "CPU wrapper" that
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Just disable all optional processor-internal modules via the according generics and you will get a "CPU wrapper" that
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provides a minimal CPU environment and an external memory interface (like AXI4). This minimal setup allows to further use
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provides a minimal CPU environment and an external memory interface (like AXI4). This minimal setup allows to further use
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the default bootloader and software framework. From this base you can start building your own processor system.
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the default bootloader and software framework. From this base you can start building your own processor system.
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*Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-spec.pdf)
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*Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-spec.pdf)
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and the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-privileged.pdf).
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and the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-privileged.pdf).
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Compatibility is checked by passing the [official RISC-V architecture tests](https://github.com/riscv/riscv-arch-test)
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Compatibility is checked by passing the [official RISC-V architecture tests](https://github.com/riscv/riscv-arch-test)
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(see [`sim/README`](sim/README.md)).
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(see [`sim/README`](sim/README.md)).
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The core implements a little-endian Von-Neumann architecture using two pipeline stages, where each stage can operate in a multi-cycle processing
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The core is a little-endian Von-Neumann machine implemented as multi-cycle architecture.
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scheme. The CPU supports three privilege levels (`machine` and optional `user` and `debug_mode`), the three standard RISC-V machine
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However, the CPU's _front end_ (instruction fetch) and _back end_ (instruction execution) can work independently to increase performance.
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Currently, three privilege levels (`machine` and optional `user` and `debug_mode`) are supported. The CPU implements all three standard RISC-V machine
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interrupts (`MTI`, `MEI`, `MSI`) plus 16 _fast interrupt requests_ as custom extensions.
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interrupts (`MTI`, `MEI`, `MSI`) plus 16 _fast interrupt requests_ as custom extensions.
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It also supports **all** standard RISC-V exceptions (instruction/load/store misaligned address & bus access fault, illegal
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It also supports **all** standard RISC-V exceptions (instruction/load/store misaligned address & bus access fault, illegal
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instruction, breakpoint, environment calls). See :books: [_"Full Virtualization"_](https://stnolting.github.io/neorv32/#_full_virtualization)
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instruction, breakpoint, environment calls).
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for more information.
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### Available ISA Extensions
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### Available ISA Extensions
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Currently, the following _optional_ RISC-V-compatible ISA extensions are implemented (linked to the according
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Currently, the following _optional_ RISC-V-compatible ISA extensions are implemented (linked to the according
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**RV32
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**RV32
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[[`I`](https://stnolting.github.io/neorv32/#_i_base_integer_isa)/
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[[`I`](https://stnolting.github.io/neorv32/#_i_base_integer_isa)/
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[`E`](https://stnolting.github.io/neorv32/#_e_embedded_cpu)]
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[`E`](https://stnolting.github.io/neorv32/#_e_embedded_cpu)]
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[[`A`](https://stnolting.github.io/neorv32/#_a_atomic_memory_access)]
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[[`A`](https://stnolting.github.io/neorv32/#_a_atomic_memory_access)]
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[[`B`](https://stnolting.github.io/neorv32/#_b_bit_manipulation_operations)]
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[[`C`](https://stnolting.github.io/neorv32/#_c_compressed_instructions)]
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[[`C`](https://stnolting.github.io/neorv32/#_c_compressed_instructions)]
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[[`M`](https://stnolting.github.io/neorv32/#_m_integer_multiplication_and_division)]
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[[`M`](https://stnolting.github.io/neorv32/#_m_integer_multiplication_and_division)]
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[[`U`](https://stnolting.github.io/neorv32/#_u_less_privileged_user_mode)]
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[[`U`](https://stnolting.github.io/neorv32/#_u_less_privileged_user_mode)]
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[[`X`](https://stnolting.github.io/neorv32/#_x_neorv32_specific_custom_extensions)]
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[[`X`](https://stnolting.github.io/neorv32/#_x_neorv32_specific_custom_extensions)]
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[[`Zbb`](https://stnolting.github.io/neorv32/#_zbb_basic_bit_manipulation_operations)]
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[[`Zfinx`](https://stnolting.github.io/neorv32/#_zfinx_single_precision_floating_point_operations)]
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[[`Zfinx`](https://stnolting.github.io/neorv32/#_zfinx_single_precision_floating_point_operations)]
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[[`Zicsr`](https://stnolting.github.io/neorv32/#_zicsr_control_and_status_register_access_privileged_architecture)]
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[[`Zicsr`](https://stnolting.github.io/neorv32/#_zicsr_control_and_status_register_access_privileged_architecture)]
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[[`Zicntr`](https://stnolting.github.io/neorv32/#_zicntr_cpu_base_counters)]
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[[`Zihpm`](https://stnolting.github.io/neorv32/#_zihpm_hardware_performance_monitors)]
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[[`Zifencei`](https://stnolting.github.io/neorv32/#_zifencei_instruction_stream_synchronization)]
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[[`Zifencei`](https://stnolting.github.io/neorv32/#_zifencei_instruction_stream_synchronization)]
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[[`Zmmul`](https://stnolting.github.io/neorv32/#_zmmul_integer_multiplication)]
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[[`Zmmul`](https://stnolting.github.io/neorv32/#_zmmul_integer_multiplication)]
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[[`PMP`](https://stnolting.github.io/neorv32/#_pmp_physical_memory_protection)]
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[[`PMP`](https://stnolting.github.io/neorv32/#_pmp_physical_memory_protection)]
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[[`HPM`](https://stnolting.github.io/neorv32/#_hpm_hardware_performance_monitors)]
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[[`DEBUG`](https://stnolting.github.io/neorv32/#_cpu_debug_mode)]**
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[[`DEBUG`](https://stnolting.github.io/neorv32/#_cpu_debug_mode)]**
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:warning: The `Zbb`, `Zfinx` and `Zmmul` RISC-V extensions are frozen but not officially ratified yet. Hence, there is no
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:warning: The `B`, `Zfinx` and `Zmmul` RISC-V extensions are frozen but not officially ratified yet. Hence, there is no
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upstream gcc support. To circumvent this, the NEORV32 software framework provides _intrinsic_ libraries for these extensions.
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upstream gcc support. To circumvent this, the NEORV32 software framework provides _intrinsic_ libraries for these extensions.
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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Results generated for hardware version [`1.5.7.10`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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Results generated for hardware version [`1.5.7.10`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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| CPU Configuration | LEs | FFs | Memory bits | DSPs (9-bit) | f_max |
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| CPU Configuration | LEs | FFs | Memory bits | DSPs (9-bit) | f_max |
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|:--------------------------------------------------|:----:|:----:|:-----------:|:------------:|:-------:|
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|:--------------------------------------------------|:----:|:----:|:-----------:|:------------:|:-------:|
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| `rv32i` | 806 | 359 | 1024 | 0 | 125 MHz |
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| `rv32i` | 806 | 359 | 1024 | 0 | 125 MHz |
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| `rv32i_Zicsr` | 1729 | 813 | 1024 | 0 | 124 MHz |
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| `rv32i_Zicsr_Zicntr` | 1729 | 813 | 1024 | 0 | 124 MHz |
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| `rv32imac_Zicsr` | 2511 | 1074 | 1024 | 0 | 124 MHz |
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| `rv32imac_Zicsr_Zicntr` | 2511 | 1074 | 1024 | 0 | 124 MHz |
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:information_source: An incremental list of CPU extension's hardware utilization can found in
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:information_source: An incremental list of CPU extension's hardware utilization can found in
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[online documentation - _"FPGA Implementation Results - CPU"_](https://stnolting.github.io/neorv32/#_cpu).
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[online documentation - _"FPGA Implementation Results - CPU"_](https://stnolting.github.io/neorv32/#_cpu).
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:information_source: The CPU provides options to further reduce the footprint (for example by constraining
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:information_source: The CPU provides options to further reduce the footprint (for example by constraining
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~~~
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~~~
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Results generated for hardware version [`1.5.7.10`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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Results generated for hardware version [`1.5.7.10`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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| CPU Configuration | CoreMark Score | CoreMarks/MHz | Average CPI |
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| CPU Configuration | CoreMark Score | CoreMarks/MHz | Average CPI |
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|:-----------------------------------------------|:--------------:|:-------------:|:-----------:|
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|:------------------------------------------------|:--------------:|:-------------:|:-----------:|
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| _small_ (`rv32i_Zicsr`) | 33.89 | **0.3389** | **4.04** |
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| _small_ (`rv32i_Zicsr`) | 33.89 | **0.3389** | **4.04** |
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| _medium_ (`rv32imc_Zicsr`) | 62.50 | **0.6250** | **5.34** |
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| _medium_ (`rv32imc_Zicsr`) | 62.50 | **0.6250** | **5.34** |
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| _performance_(`rv32imc_Zicsr` + perf. options) | 95.23 | **0.9523** | **3.54** |
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| _performance_(`rv32imc_Zicsr` + perf. options) | 95.23 | **0.9523** | **3.54** |
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:information_source: More information regarding the CPU performance can be found in the
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:information_source: More information regarding the CPU performance can be found in the
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* [SoC Modules](https://stnolting.github.io/neorv32/#_processor_internal_modules) - available IO/peripheral modules and memories
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* [SoC Modules](https://stnolting.github.io/neorv32/#_processor_internal_modules) - available IO/peripheral modules and memories
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* [On-Chip Debugger](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd) - online & in-system debugging of the processor via JTAG
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* [On-Chip Debugger](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd) - online & in-system debugging of the processor via JTAG
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* [NEORV32 CPU](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu) - the CPU
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* [NEORV32 CPU](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu) - the CPU
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* [RISC-V compatibility](https://stnolting.github.io/neorv32/#_risc_v_compatibility) - what is compatible to the specs. and what is not
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* [RISC-V compatibility](https://stnolting.github.io/neorv32/#_risc_v_compatibility) - what is compatible to the specs. and what is not
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* [Full Virtualization](https://stnolting.github.io/neorv32/#_full_virtualization) - hardware execution safety
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* [ISA and Extensions](https://stnolting.github.io/neorv32/#_instruction_sets_and_extensions) - available RISC-V ISA extensions
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* [ISA and Extensions](https://stnolting.github.io/neorv32/#_instruction_sets_and_extensions) - available RISC-V ISA extensions
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* [CSRs](https://stnolting.github.io/neorv32/#_control_and_status_registers_csrs) - control and status registers
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* [CSRs](https://stnolting.github.io/neorv32/#_control_and_status_registers_csrs) - control and status registers
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* [Traps](https://stnolting.github.io/neorv32/#_traps_exceptions_and_interrupts) - interrupts and exceptions
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* [Traps](https://stnolting.github.io/neorv32/#_traps_exceptions_and_interrupts) - interrupts and exceptions
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### :floppy_disk: Software Overview
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### :floppy_disk: Software Overview
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