| Line 57... |
Line 57... |
### Status
|
### Status
|
|
|
The processor is synthesizable (tested with Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/LSE) and can successfully execute
|
The processor is synthesizable (tested with Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/LSE) and can successfully execute
|
all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the CoreMark benchmark.
|
all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the CoreMark benchmark.
|
|
|
The processor passes the `rv32i`, `rv32im`, `rv32imc` and `rv32Zicsr` *RISC-V compliance tests*.
|
The processor passes the official `rv32i`, `rv32im`, `rv32imc` and `rv32Zicsr` [RISC-V compliance tests](https://github.com/riscv/riscv-compliance).
|
|
|
|
| | |
|
|
|:--------------------------------------------------------------------------------|:-------|
|
|
| [Pre-build toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) | [](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) |
|
|
| [RISC-V compliance test](https://github.com/stnolting/neorv32_compliance_test) | [](https://travis-ci.com/stnolting/neorv32_riscv_compliance) |
|
|
|
|
|
|
#### Limitations to be fixed
|
|
|
|
* No exception is triggered in `E`-mode when using registers above `x15` yet
|
|
|
|
|
|
#### To-Do / Wish List
|
|
|
|
- Port Dhrystone benchmark
|
|
- Implement atomic operations (`A` extension)
|
|
- Implement `Zifence` extension
|
|
- Implement co-processor for single-precision floating-point operations (`F` extension)
|
|
- Implement user mode (`U` extension)
|
|
- Make a 64-bit branch
|
|
- Maybe port an RTOS (like [freeRTOS](https://www.freertos.org/) or [RIOT](https://www.riot-os.org/))
|
|
|
[RISC-V compliance test](https://github.com/stnolting/neorv32_compliance_test):
|
|
[](https://travis-ci.com/stnolting/neorv32_riscv_compliance)
|
|
|
|
|
|
## Features
|
## Features
|
|
|
|
|
| Line 76... |
Line 95... |
- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
|
- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
|
- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework
|
- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework
|
- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc.
|
- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc.
|
- Fully synchronous design, no latches, no gated clocks
|
- Fully synchronous design, no latches, no gated clocks
|
- Small hardware footprint and high operating frequency
|
- Small hardware footprint and high operating frequency
|
- Customizable processor configuration
|
- Highly customizable processor configuration
|
- Optional processor-internal data and instruction memories (DMEM/IMEM)
|
- Optional processor-internal data and instruction memories (DMEM/IMEM)
|
- Optional internal bootloader with UART console and automatic SPI flash boot option
|
- _Optional_ internal bootloader with UART console and automatic SPI flash boot option
|
- Optional machine system timer (MTIME), RISC-V-compliant
|
- _Optional_ machine system timer (MTIME), RISC-V-compliant
|
- Optional universal asynchronous receiver and transmitter (UART)
|
- _Optional_ universal asynchronous receiver and transmitter (UART)
|
- Optional 8/16/24/32-bit serial peripheral interface master (SPI) with 8 dedicated chip select lines
|
- _Optional_ 8/16/24/32-bit serial peripheral interface controller (SPI) with 8 dedicated chip select lines
|
- Optional two wire serial interface master (TWI), compatible to the I²C standard
|
- _Optional_ two wire serial interface controller (TWI), compatible to the I²C standard
|
- Optional general purpose parallel IO port (GPIO), 16xOut & 16xIn, with pin-change interrupt
|
- _Optional_ general purpose parallel IO port (GPIO), 16xOut & 16xIn, with pin-change interrupt
|
- Optional 32-bit external bus interface, Wishbone b4 compliant (WISHBONE)
|
- _Optional_ 32-bit external bus interface, Wishbone b4 compliant (WISHBONE)
|
- Optional watchdog timer (WDT)
|
- _Optional_ watchdog timer (WDT)
|
- Optional PWM controller with 4 channels and 8-bit duty cycle resolution (PWM)
|
- _Optional_ PWM controller with 4 channels and 8-bit duty cycle resolution (PWM)
|
- Optional GARO-based true random number generator (TRNG)
|
- _Optional_ GARO-based true random number generator (TRNG)
|
- Optional core-local interrupt controller with 8 channels (CLIC)
|
- _Optional_ core-local interrupt controller with 8 channels (CLIC)
|
- Optional dummy device (DEVNULL) (can be used for *fast* simulation console output)
|
- _Optional_ dummy device (DEVNULL) (can be used for *fast* simulation console output)
|
|
|
|
|
### CPU Features
|
### CPU Features
|
|
|
The CPU is compliant to the [official RISC-V specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the
|
The CPU is compliant to the [official RISC-V specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the
|
[RISC-V privileged architecture specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf).
|
[RISC-V privileged architecture specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf).
|
|
|
**RV32I base instruction set** (`I` extension):
|
**RV32I base instruction set** (`I` extension):
|
* ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND`
|
* ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND`
|
* Branches instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
|
* Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
|
* Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW`
|
* Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW`
|
|
|
**Compressed instructions** (`C` extension):
|
**Compressed instructions** (`C` extension):
|
* ALU instructions: `C.ADDI4SPN` `C.ADDI` `C.ADD` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP`
|
* ALU instructions: `C.ADDI4SPN` `C.ADDI` `C.ADD` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP`
|
* Branches instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ`
|
* Jump and branch instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ`
|
* Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP`
|
* Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP`
|
* Misc instructions: `C.EBREAK` (only with `Zicsr` extension)
|
* Misc instructions: `C.EBREAK` (only with `Zicsr` extension)
|
|
|
**Embedded CPU version** (`E` extension):
|
**Embedded CPU version** (`E` extension):
|
* Reduced register file (only the 16 lowest registers)
|
* Reduced register file (only the 16 lowest registers)
|
| Line 121... |
Line 140... |
**Privileged architecture** (`Zicsr` extension):
|
**Privileged architecture** (`Zicsr` extension):
|
* Privilege levels: `M-mode` (Machine mode)
|
* Privilege levels: `M-mode` (Machine mode)
|
* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
|
* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
|
* System instructions: `ECALL` `EBREAK` `MRET` `WFI`
|
* System instructions: `ECALL` `EBREAK` `MRET` `WFI`
|
* Counter CSRs: `cycle` `cycleh` `time` `timeh` `instret` `instreth` `mcycle` `mcycleh` `minstret` `minstreth`
|
* Counter CSRs: `cycle` `cycleh` `time` `timeh` `instret` `instreth` `mcycle` `mcycleh` `minstret` `minstreth`
|
* Machine CSRs: `mstatus` `misa` `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mtinst` `mimpid` `mhartid`
|
* Machine CSRs: `mstatus` `misa` `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mimpid` `mhartid`
|
* Custom CSRs: `mfeatures` `mclock` `mispacebase` `mdspacebase` `mispacesize` `mdspacesize`
|
* Custom CSRs: `mfeatures` `mclock` `mispacebase` `mdspacebase` `mispacesize` `mdspacesize`
|
* Supported exceptions and interrupts:
|
* Supported exceptions and interrupts:
|
* Misaligned instruction address
|
* Misaligned instruction address
|
* Instruction access fault
|
* Instruction access fault
|
* Illegal instruction
|
* Illegal instruction
|
| Line 145... |
Line 164... |
|
|
More information including a detailed list of the available CSRs can be found in
|
More information including a detailed list of the available CSRs can be found in
|
the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
|
|
|
|
### To-Do / Wish List
|
|
|
|
- No exception is triggered in `E`-mode when using reg >x15 yet
|
|
- Port Dhrystone benchmark
|
|
- Implement atomic operations (`A` extension)
|
|
- Implement `Zifence` extension
|
|
- Implement co-processor for single-precision floating-point operations (`F` extension)
|
|
- Implement user mode (`U` extension)
|
|
- Make a 64-bit branch
|
|
- Maybe port an RTOS (like [freeRTOS](https://www.freertos.org/) or [RIOT](https://www.riot-os.org/))
|
|
|
|
|
|
|
|
## FPGA Implementation Results
|
## FPGA Implementation Results
|
|
|
This chapter shows exemplary implementation results of the NEORV32 processor for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
|
This chapter shows exemplary implementation results of the NEORV32 processor for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
|
a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing
|
a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing
|
