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=== RISC-V Compatibility
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=== RISC-V Compatibility
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The NEORV32 CPU passes the rv32_m/I, rv32_m/M, rv32_m/C, rv32_m/privilege, and
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The NEORV32 CPU passes the rv32_m/I, rv32_m/M, rv32_m/C, rv32_m/privilege, and
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rv32_m/Zifencei tests of the official RISC-V Architecture Tests (GitHub). The port files for the
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rv32_m/Zifencei tests of the official RISC-V Architecture Tests (GitHub). The port files for the
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NEORV32 processor are located in the repository's `riscv-arch-test` folder. See section <<_risc_v_architecture_test_framework>>
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NEORV32 processor are located in the repository's `sw/isa-test` folder.
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[NOTE]
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See section https://stnolting.github.io/neorv32/ug/#_risc_v_architecture_test_framework[User Guide: RISC-V Architecture Test Framework]
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for information how to run the tests on the NEORV32.
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for information how to run the tests on the NEORV32.
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.**RISC-V `rv32_m/C` Tests**
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.**RISC-V `rv32_m/C` Tests**
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...................................
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...................................
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Check cadd-01 ... OK
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Check cadd-01 ... OK
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A custom CSR `mzext` is available that can be used to check for implemented `Z*` CPU extensions
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A custom CSR `mzext` is available that can be used to check for implemented `Z*` CPU extensions
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(for example `Zifencei`). This CSR is mapped to the official "custom CSR address region".
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(for example `Zifencei`). This CSR is mapped to the official "custom CSR address region".
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[NOTE]
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[NOTE]
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All undefined/unimplemented/malformed/illegal instructions do raise an illegal instruction exception
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All undefined/unimplemented/malformed/illegal instructions do raise an illegal instruction exception
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(see <<_execution_safety>>).
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(see <<_full_virtualization>>).
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==== **`Zfinx`** Single-Precision Floating-Point Operations
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==== **`Zfinx`** Single-Precision Floating-Point Operations
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The `Zfinx` floating-point extension is an alternative of the `F` floating-point instruction that also uses the
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The `Zfinx` floating-point extension is an alternative of the `F` floating-point instruction that also uses the
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The `Zfinx` extension is not yet officially ratified, but is expected to stay unchanged. There is no
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The `Zfinx` extension is not yet officially ratified, but is expected to stay unchanged. There is no
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software support for the `Zfinx` extension in the upstream GCC RISC-V port yet. However, an
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software support for the `Zfinx` extension in the upstream GCC RISC-V port yet. However, an
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intrinsic library is provided to utilize the provided `Zfinx` floating-point extension from C-language
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intrinsic library is provided to utilize the provided `Zfinx` floating-point extension from C-language
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code (see `sw/example/floating_point_test`).
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code (see `sw/example/floating_point_test`).
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[IMPORTANT]
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Note that any FPU instruction including all FPU-related CSR accesses will raise an illegal instruction exception
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if the FPU is not enabled via the <<_mstatus>> CSR (`FS` bits).
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==== **`Zicsr`** Control and Status Register Access / Privileged Architecture
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==== **`Zicsr`** Control and Status Register Access / Privileged Architecture
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The CSR access instructions as well as the exception and interrupt system (= the privileged architecture) is implemented when the
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The CSR access instructions as well as the exception and interrupt system (= the privileged architecture) is implemented when the
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`CPU_EXTENSION_RISCV_Zicsr` configuration generic is _true_. In this case the following instructions are
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`CPU_EXTENSION_RISCV_Zicsr` configuration generic is _true_. In this case the following instructions are
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[NOTE]
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[NOTE]
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The "wait for interrupt instruction" `wfi` works like a sleep command. When executed, the CPU is
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The "wait for interrupt instruction" `wfi` works like a sleep command. When executed, the CPU is
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halted until a valid interrupt request occurs. To wake up again, the according interrupt source has to
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halted until a valid interrupt request occurs. To wake up again, the according interrupt source has to
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be enabled via the `mie` CSR and the global interrupt enable flag in `mstatus` has to be set.
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be enabled via the `mie` CSR and the global interrupt enable flag in `mstatus` has to be set.
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[IMPORTANT]
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The `wfi` instruction will raise an illegal instruction exception when executed outside of machine-mode
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and <<_mstatus>> bit `TW` (timeout wait) is set.
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==== **`Zifencei`** Instruction Stream Synchronization
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==== **`Zifencei`** Instruction Stream Synchronization
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The `Zifencei` CPU extension is implemented if the `CPU_EXTENSION_RISCV_Zifencei` configuration
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The `Zifencei` CPU extension is implemented if the `CPU_EXTENSION_RISCV_Zifencei` configuration
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generic is _true_. It allows manual synchronization of the instruction stream via the following instruction:
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generic is _true_. It allows manual synchronization of the instruction stream via the following instruction:
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N-bit wide counter (split in a high-word 32-bit CSR and a low-word 32-bit CSR), where N is defined via the top's
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N-bit wide counter (split in a high-word 32-bit CSR and a low-word 32-bit CSR), where N is defined via the top's
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`HPM_CNT_WIDTH` generic (0..64-bit), and a corresponding event configuration CSR. The event configuration
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`HPM_CNT_WIDTH` generic (0..64-bit), and a corresponding event configuration CSR. The event configuration
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CSR defines the architectural events that lead to an increment of the associated HPM counter.
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CSR defines the architectural events that lead to an increment of the associated HPM counter.
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The cycle, time and instructions-retired counters (`[m]cycle[h]`, `time[h]`, `[m]instret[h]`) are
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The cycle, time and instructions-retired counters (`[m]cycle[h]`, `time[h]`, `[m]instret[h]`) are
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mandatory performance monitors on every RISC-V platform and have fixed increment event. For example,
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mandatory performance monitors on every RISC-V platform and have fixed increment events. For example,
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the instructions-retired counter increments with each executed instructions. The actual hardware performance
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the instructions-retired counter increments with each executed instructions. The actual hardware performance
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monitors are optional and can be configured to increment on arbitrary hardware events. The number of
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monitors are optional and can be configured to increment on arbitrary hardware events. The number of
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available HPM is configured via the top's `HPM_NUM_CNTS` generic at synthesis time. Assigning a zero will exclude
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available HPM is configured via the top's `HPM_NUM_CNTS` generic at synthesis time. Assigning a zero will exclude
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all HPM logic from the design.
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all HPM logic from the design.
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Depending on the configuration, the following additional CSR are available:
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Depending on the configuration, the following additional CSR are available:
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* counters: `[m]hpmcounter*[h]` (3..31, depending on configuration)
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* counters: `mhpmcounter*[h]` (3..31, depending on configuration)
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* event configuration: `mhpmevent*` (3..31, depending on configuration)
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* event configuration: `mhpmevent*` (3..31, depending on configuration)
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User-level access to the counter registers `hpmcounter*[h]` can be individually restricted via the `mcounteren` CSR.
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[IMPORTANT]
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The HPM counter CSR can only be accessed in machine-mode. Hence, the according `mcounteren` CSR bits
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are always zero and read-only.
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Auto-increment of the HPMs can be individually deactivated via the `mcountinhibit` CSR.
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Auto-increment of the HPMs can be individually deactivated via the `mcountinhibit` CSR.
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If `HPM_NUM_CNTS` is lower than the maximumg value (=29) the remaining HPMs are not implemented.
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If `HPM_NUM_CNTS` is lower than the maximum value (=29) the remaining HPM CSRs are not implemented and the
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However, accessing their associated CSRs will not raise an illegal instructions exception. These CSR are
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according `mcountinhibit` CSR bits are hardwired to zero.
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read-only and will always return 0.
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However, accessing their associated CSRs will not raise an illegal instruction exception (if in machine mode).
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The according CSRs are read-only and will always return 0.
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[NOTE]
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[NOTE]
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For a list of all allocated HPM-related CSRs and all provided event configurations see section <<_hardware_performance_monitors_hpm>>.
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For a list of all allocated HPM-related CSRs and all provided event configurations see section <<_hardware_performance_monitors_hpm>>.
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// ####################################################################################################################
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// ####################################################################################################################
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==== Execution Safety
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==== Full Virtualization
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The hardware of the NEORV32 CPU was designed for maximum *execution safety*. If the `Zicsr` CPU
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extension is enabled, the core supports **all** traps specified by the official RISC-V specifications (obviously,
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not the ones that are related to yet unimplemented extensions/features). Thus, the CPU provides well-defined
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hardware fall-backs for (nearly) everything that can go wrong. Even if any kind of trap is triggered, the core
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is always in a defined and fully synchronized state throughout the whole architecture (i.e. no need to make
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out-of-order operations undone) that allows predictable execution behavior at any time.
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**Core Safety Features**
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* Due to the acknowledged memory accesses the CPU is _always_ sync with the memory system (no speculative execution / out-of-order states).
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* The CPU supports all bus exceptions including bus access exceptions that are triggered if an
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accessed address does not respond or encounters an internal error during access (which is a rare
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feature in many open-source RISC-V cores).
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* The CPU raises an illegal instruction trap for **all** unimplemented/malformed/illegal instructions (to support _full_ virtualization).
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* If user-level code tries to read from machine-level-only CSRs (like `mstatus`) an illegal instruction
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exception is raised. The results of this operations is always zero (though, machine-level
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code handling this exception can modify the target register of the illegal access-causing
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instruction to allow full virtualization). Illegal write accesses to machine CSRs will not be write any data at all.
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* Illegal user-level memory accesses to protected addresses or address regions (via physical memory
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protection) will not be conducted at all (no actual write and no actual read; prevents triggering of
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memory-mapped devices). Illegal load operations will not return any data (the instruction's
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destination register will not be written at all).
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Just like the RISC-V ISA the NEORV32 aims to support _ maximum virtualization_ capabilities
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on CPU _and_ SoC level. The CPU supports **all** traps specified by the official RISC-V specifications.footnote:[If the `Zicsr` CPU
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extension is enabled (implementing the full set of the privileged architecture).]
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Thus, the CPU provides defined hardware fall-backs for any expected and unexpected situation (e.g. executing an
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malformed instruction word or accessing a not-allocated address). For any kind of trap the core is always in a
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defined and fully synchronized state throughout the whole architecture (i.e. there are no out-of-order operations that
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have to be made undone). This allows predictable execution behavior - and thus, defined operations to resolve the cause
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of the trap - at any time improving overall _execution safety_.
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**NEORV32-Specific Virtualization Features**
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* Due to the acknowledged memory accesses the CPU is _always_ sync with the memory system
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(i.e. there is no speculative execution / no out-of-order states).
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* The CPU supports _all_ RISC-V bus exceptions including access exceptions that are triggered if an
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accessed address does not respond or encounters an internal error during access.
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* The CPU raises an illegal instruction trap for _all_ unimplemented/malformed/illegal instructions.
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* To be continued...
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// ####################################################################################################################
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// ####################################################################################################################
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