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** `C` - 16-bit compressed instructions
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** `C` - 16-bit compressed instructions
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** `I` - integer base ISA (always enabled)
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** `I` - integer base ISA (always enabled)
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** `E` - embedded CPU version (reduced register file size)
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** `E` - embedded CPU version (reduced register file size)
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** `M` - integer multiplication and division hardware
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** `M` - integer multiplication and division hardware
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** `U` - less-privileged _user_ mode
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** `U` - less-privileged _user_ mode
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** `Zbb` - basic bit-manipulation operations
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** `Zfinx` - single-precision floating-point unit
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** `Zfinx` - single-precision floating-point unit
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** `Zicsr` - control and status register access (privileged architecture)
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** `Zicsr` - control and status register access (privileged architecture)
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** `Zifencei` - instruction stream synchronization
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** `Zifencei` - instruction stream synchronization
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** `Zmmul` - integer multiplication hardware
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** `Zmmul` - integer multiplication hardware
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** `PMP` - physical memory protection
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** `PMP` - physical memory protection
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(instruction set architecture) extensions. For more information regarding the RISC-V ISA extensions please
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(instruction set architecture) extensions. For more information regarding the RISC-V ISA extensions please
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see the The _RISC-V Instruction Set Manual – Volume I: Unprivileged ISA_ and _The RISC-V Instruction Set Manual
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see the The _RISC-V Instruction Set Manual – Volume I: Unprivileged ISA_ and _The RISC-V Instruction Set Manual
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Volume II: Privileged Architecture_, which are available in the projects `docs/references` folder.
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Volume II: Privileged Architecture_, which are available in the projects `docs/references` folder.
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[TIP]
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[TIP]
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The CPU can discover available ISA extensions via the <<_misa>> and <<_mzext>> CSRs or by executing an instruction
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The CPU can discover available ISA extensions via the <<_misa>> CSR and the
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and checking for an _illegal instruction exception_.
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_SYSINFO_CPU_ <<_system_configuration_information_memory_sysinfo, SYSINFO>> register
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or by executing an instruction and checking for an _illegal instruction exception_.
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[NOTE]
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Executing an instruction from an extension that is not implemented or not enabled (for example via the according
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top entity generic) will raise an _illegal instruction_ exception.
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==== **`A`** - Atomic Memory Access
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==== **`A`** - Atomic Memory Access
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Atomic memory access instructions (for implementing semaphores and mutexes) are available when the
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Atomic memory access instructions (for implementing semaphores and mutexes) are available when the
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The embedded CPU extensions reduces the size of the general purpose register file from 32 entries to 16 entries to reduce hardware
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The embedded CPU extensions reduces the size of the general purpose register file from 32 entries to 16 entries to reduce hardware
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requirements. This extensions is enabled when the `CPU_EXTENSION_RISCV_E` configuration generic is _true_. Accesses to registers beyond
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requirements. This extensions is enabled when the `CPU_EXTENSION_RISCV_E` configuration generic is _true_. Accesses to registers beyond
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`x15` will raise and _illegal instruction exception_.
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`x15` will raise and _illegal instruction exception_.
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Due to the reduced register file an alternate ABI (**`ilp32e`**) is required for the toolchain.
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[IMPORTANT]
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Due to the reduced register file size an alternate toolchain ABI (**`ilp32e`**) is required.
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==== **`I`** - Base Integer ISA
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==== **`I`** - Base Integer ISA
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The CPU always supports the complete `rv32i` base integer instruction set. This base set is always enabled
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The CPU always supports the complete `rv32i` base integer instruction set. This base set is always enabled
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regardless of the setting of the remaining exceptions. The base instruction set includes the following
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regardless of the setting of the remaining exceptions. The base instruction set includes the following
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integer multiplications but not hardware-based divisions, which will be computed entirely in software.
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integer multiplications but not hardware-based divisions, which will be computed entirely in software.
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This extension requires only ~50% of the hardware utilization of the `M` extension.
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This extension requires only ~50% of the hardware utilization of the `M` extension.
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* multiplication: `mul`, `mulh`, `mulhsu`, `mulhu`
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* multiplication: `mul`, `mulh`, `mulhsu`, `mulhu`
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If `Zmmul` is enabled, executing any division instruction from the `M` ISA (`div`, `divu`, `rem`, `remu`)
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If `Zmmul` is enabled, executing any division instruction from the `M` ISA extension (`div`, `divu`, `rem`, `remu`)
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will raise an illegal instruction exception.
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will raise an _illegal instruction exception_.
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Note that `M` and `Zmmul` extensions _cannot_ be enabled in parallel.
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Note that `M` and `Zmmul` extensions _cannot_ be enabled at the same time.
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[TIP]
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[TIP]
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If your RISC-V GCC toolchain does not (yet) support the `_Zmmul` ISA extensions, it can be "emulated"
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If your RISC-V GCC toolchain does not (yet) support the `_Zmmul` ISA extensions, it can be "emulated"
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using a `rv32im` machine architecture and setting the `-mno-div` compiler flag
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using a `rv32im` machine architecture and setting the `-mno-div` compiler flag
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(example `$ make MARCH=-march=rv32im USER_FLAGS+=-mno-div clean_all exe`).
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(example `$ make MARCH=-march=rv32im USER_FLAGS+=-mno-div clean_all exe`).
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==== **`U`** - Less-Privileged User Mode
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==== **`U`** - Less-Privileged User Mode
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Adds the less-privileged _user mode_ when the `CPU_EXTENSION_RISCV_U` configuration generic is _true_. For
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Adds the less-privileged _user mode_ if the `CPU_EXTENSION_RISCV_U` configuration generic is _true_. For
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instance, use-level code cannot access machine-mode CSRs. Furthermore, access to the address space (like
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instance, use-level code cannot access machine-mode CSRs. Furthermore, access to the address space (like
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peripheral/IO devices) can be limited via the physical memory protection (_PMP_) unit for code running in user mode.
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peripheral/IO devices) can be limited via the physical memory protection (_PMP_) unit for code running in user mode.
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==== **`X`** - NEORV32-Specific (Custom) Extensions
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==== **`X`** - NEORV32-Specific (Custom) Extensions
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The NEORV32-specific extensions are always enabled and are indicated by the set `X` bit in the `misa` CSR.
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The NEORV32-specific extensions are always enabled and are indicated by the set `X` bit in the `misa` CSR.
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[NOTE]
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The most important points of the NEORV32-specific extensions are:
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The CPU provides 16 _fast interrupt_ interrupts (`FIRQ)`, which are controlled via custom bits in the `mie`
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* The CPU provides 16 _fast interrupt_ interrupts (`FIRQ)`, which are controlled via custom bits in the `mie`
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and `mip` CSR. This extension is mapped to bits, that are available for custom use (according to the
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and `mip` CSR. This extension is mapped to bits, that are available for custom use (according to the
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RISC-V specs). Also, custom trap codes for `mcause` are implemented.
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RISC-V specs). Also, custom trap codes for `mcause` are implemented.
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* The CPU provides a single _non-maskable_ interrupt (`NMI)` that also provides a custom trap code for `mcause`.
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[NOTE]
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* All undefined/unimplemented/malformed/illegal instructions do raise an illegal instruction exception (see <<_full_virtualization>>).
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The CPU provides a single _non-maskable_ interrupt (`NMI)` that also provides a custom trap code for `mcause`.
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[NOTE]
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A custom CSR `mzext` is available that can be used to check for implemented `Z*` CPU extensions
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(for example `Zifencei`). This CSR is mapped to the official "custom CSR address region".
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[NOTE]
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All undefined/unimplemented/malformed/illegal instructions do raise an illegal instruction exception
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(see <<_full_virtualization>>).
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==== **`Zfinx`** Single-Precision Floating-Point Operations
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==== **`Zfinx`** Single-Precision Floating-Point Operations
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[WARNING]
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The NEORV32 `Zfinx` extension is specification-compliant and operational but still _experimental_.
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The `Zfinx` floating-point extension is an alternative of the `F` floating-point instruction that also uses the
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The `Zfinx` floating-point extension is an alternative of the `F` floating-point instruction that also uses the
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integer register file `x` to store and operate on floating-point data (hence, `F-in-x`). Since not dedicated floating-point `f`
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integer register file `x` to store and operate on floating-point data (hence, `F-in-x`). Since not dedicated floating-point `f`
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register file exists, the `Zfinx` extension requires less hardware resources and features faster context changes.
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register file exists, the `Zfinx` extension requires less hardware resources and features faster context changes.
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This also implies that there are NO dedicated `f` register file related load/store or move instructions. The
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This also implies that there are NO dedicated `f` register file related load/store or move instructions. The
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official RISC-V specifications can be found here: https://github.com/riscv/riscv-zfinx
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official RISC-V specifications can be found here: https://github.com/riscv/riscv-zfinx
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The `Zfinx` extension is not yet officially ratified, but is expected to stay unchanged. There is no
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The `Zfinx` extension is not yet officially ratified, but is expected to stay unchanged. There is no
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software support for the `Zfinx` extension in the upstream GCC RISC-V port yet. However, an
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software support for the `Zfinx` extension in the upstream GCC RISC-V port yet. However, an
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intrinsic library is provided to utilize the provided `Zfinx` floating-point extension from C-language
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intrinsic library is provided to utilize the provided `Zfinx` floating-point extension from C-language
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code (see `sw/example/floating_point_test`).
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code (see `sw/example/floating_point_test`).
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==== **`Zbb`** Basic Bit-Manipulation Operations
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[WARNING]
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The NEORV32 `Zbb` extension is specification-compliant and operational but still _experimental_.
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The `Zbb` extension implements the _basic_ sub-set of the RISC-V bit-manipulation extensions `B`.
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The official RISC-V specifications can be found here: https://github.com/riscv/riscv-bitmanip
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The `Zbb` extension is implemented when the `CPU_EXTENSION_RISCV_Zbb` configuration
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generic is _true_. In this case the following instructions are available:
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* `andn`, `orn`, `xnor`
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* `clz`, `ctz`, `cpop`
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* `max`, `maxu`, `min`, `minu`
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* `sext.b`, `sext.h`, `zext.h`
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* `rol`, `ror`, `rori`
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* `orc.b`, `rev8`
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[TIP]
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By default, the bit-manipulation unit uses an _iterative_ approach to compute shift-related operations
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like `clz` and `rol`. To increase performance (at the cost of additional hardware resources) the
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<<_fast_shift_en>> generic can be enabled to implement full-parallel logic (like barrel shifters) for all
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shift-related `Zbb` instructions.
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[IMPORTANT]
|
[IMPORTANT]
|
Note that any FPU instruction including all FPU-related CSR accesses will raise an illegal instruction exception
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The `Zbb` extension is frozen but not officially ratified yet. There is no
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if the FPU is not enabled via the <<_mstatus>> CSR (`FS` bits).
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software support for this extension in the upstream GCC RISC-V port yet. However, an
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intrinsic library is provided to utilize the provided `Zbb` extension from C-language
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code (see `sw/example/bitmanip_test`).
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==== **`Zicsr`** Control and Status Register Access / Privileged Architecture
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==== **`Zicsr`** Control and Status Register Access / Privileged Architecture
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The CSR access instructions as well as the exception and interrupt system (= the privileged architecture) is implemented when the
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The CSR access instructions as well as the exception and interrupt system (= the privileged architecture) is implemented when the
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Line 732... |
| Floating-point - artihmetic | `Zfinx` | `fmul.s` | 22
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| Floating-point - artihmetic | `Zfinx` | `fmul.s` | 22
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| Floating-point - compare | `Zfinx` | `fmin.s` `fmax.s` `feq.s` `flt.s` `fle.s` | 13
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| Floating-point - compare | `Zfinx` | `fmin.s` `fmax.s` `feq.s` `flt.s` `fle.s` | 13
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| Floating-point - misc | `Zfinx` | `fsgnj.s` `fsgnjn.s` `fsgnjx.s` `fclass.s` | 12
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| Floating-point - misc | `Zfinx` | `fsgnj.s` `fsgnjn.s` `fsgnjx.s` `fclass.s` | 12
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| Floating-point - conversion | `Zfinx` | `fcvt.w.s` `fcvt.wu.s` | 47
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| Floating-point - conversion | `Zfinx` | `fcvt.w.s` `fcvt.wu.s` | 47
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| Floating-point - conversion | `Zfinx` | `fcvt.s.w` `fcvt.s.wu` | 48
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| Floating-point - conversion | `Zfinx` | `fcvt.s.w` `fcvt.s.wu` | 48
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| Basic bit-manip - logic | `Zbb` | `andn` `orn` `xnor` | 3
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| Basic bit-manip - shift | `Zbb` | `clz` `ctz` `cpop` `rol` `ror` `rori` | 4+SA, FAST_SHIFT: 4
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| Basic bit-manip - arith | `Zbb` | `max` `maxu` `min` `minu` | 3
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| Basic bit-manip - misc | `Zbb` | `sext.b` `sext.h` `zext.h` `orc.b` `rev8` | 3
|
|=======================
|
|=======================
|
|
|
[NOTE]
|
[NOTE]
|
The presented values of the *floating-point execution cycles* are average values – obtained from
|
The presented values of the *floating-point execution cycles* are average values – obtained from
|
4096 instruction executions using pseudo-random input values. The execution time for emulating the
|
4096 instruction executions using pseudo-random input values. The execution time for emulating the
|
