| Line 29... |
Line 29... |
* Optional hardware performance monitors (HPM) for application benchmarking
|
* Optional hardware performance monitors (HPM) for application benchmarking
|
* Separated interfaces for instruction fetch and data access (merged into single bus via a bus switch for
|
* Separated interfaces for instruction fetch and data access (merged into single bus via a bus switch for
|
the NEORV32 processor)
|
the NEORV32 processor)
|
* little-endian byte order
|
* little-endian byte order
|
* Configurable hardware reset
|
* Configurable hardware reset
|
* No hardware support of unaligned data/instruction accesses – they will trigger an exception. If the C extension is enabled instructions
|
* No hardware support of unaligned data/instruction accesses – they will trigger an exception.
|
can also be 16-bit aligned and a misaligned instruction address exception is not possible anymore
|
|
|
|
[NOTE]
|
[NOTE]
|
It is recommended to use the **NEORV32 Processor** as default top instance even if you only want to use the actual
|
It is recommended to use the **NEORV32 Processor** as default top instance even if you only want to use the actual
|
CPU. Simply disable all the processor-internal modules via the generics and you will get a "CPU
|
CPU. Simply disable all the processor-internal modules via the generics and you will get a "CPU
|
wrapper" that provides a minimal CPU environment and an external bus interface (like AXI4). This
|
wrapper" that provides a minimal CPU environment and an external bus interface (like AXI4). This
|
| Line 215... |
Line 214... |
|
|
|
|
:sectnums:
|
:sectnums:
|
==== RISC-V Incompatibility Issues and Limitations
|
==== RISC-V Incompatibility Issues and Limitations
|
|
|
This list shows the currently known issues regarding full RISC-V-compatibility. More specific information
|
This list shows the currently identified issues regarding full RISC-V-compatibility. More specific information
|
can be found in section <<_instruction_sets_and_extensions>>.
|
can be found in section <<_instruction_sets_and_extensions>>.
|
|
|
|
.Hardwired R/W CSRs
|
[IMPORTANT]
|
[IMPORTANT]
|
The `misa` CSR is read-only. It shows the synthesized CPU extensions. Hence, all implemented
|
The `misa`, `mip` and `mtval` CSRs in the NEORV32 are _read-only_.
|
CPU extensions are always active and cannot be enabled/disabled dynamically during runtime. Any
|
Any write access to it (in machine mode) to them are ignored and will _not_ cause any exceptions or side-effects.
|
write access to it (in machine mode) is ignored and will not cause any exception or side-effects.
|
|
|
|
[IMPORTANT]
|
|
The `mip` CSR is read-only. Pending IRQs can be cleared using the `mie` CSR.
|
|
|
|
[IMPORTANT]
|
|
The `mtval` CSR is read-only.
|
|
|
|
|
.Physical memory protection
|
[IMPORTANT]
|
[IMPORTANT]
|
The physical memory protection (see section <<_machine_physical_memory_protection>>)
|
The physical memory protection (see section <<_machine_physical_memory_protection>>)
|
only supports the modes _OFF_ and _NAPOT_ yet and a minimal granularity of 8 bytes per region.
|
only supports the modes _OFF_ and _NAPOT_ yet and a minimal granularity of 8 bytes per region.
|
|
|
|
.Atomic memory operations
|
[IMPORTANT]
|
[IMPORTANT]
|
The `A` CPU extension (atomic memory access) only implements the `lr.w` and `sc.w` instructions yet.
|
The `A` CPU extension only implements the `lr.w` and `sc.w` instructions yet.
|
However, these instructions are sufficient to emulate all further AMO operations.
|
However, these instructions are sufficient to emulate all further atomic memory operations.
|
|
|
|
.Instruction Misalignment
|
|
[NOTE]
|
|
This is not a real RISC-V incompatibility, but something that might not be clear when studying the RISC-V privileged
|
|
architecture specifications: for 32-bit only instructions (no `C` extension) the misaligned instruction exception
|
|
is raised if bit 1 of the access address is set (i.e. not on 32-bit boundary). If the `C` extension is implemented
|
|
there will be no misaligned instruction exceptions _at all_.
|
|
In both cases bit 0 of the program counter and all related registers is hardwired to zero.
|
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
| Line 282... |
Line 285... |
| `d_bus_err_i` | 1 | in | bus transfer terminate from accessed peripheral
|
| `d_bus_err_i` | 1 | in | bus transfer terminate from accessed peripheral
|
| `d_bus_fence_o` | 1 | out | indicates an executed _fence_ instruction
|
| `d_bus_fence_o` | 1 | out | indicates an executed _fence_ instruction
|
| `d_bus_priv_o` | 2 | out | current CPU privilege level
|
| `d_bus_priv_o` | 2 | out | current CPU privilege level
|
4+^| **System Time (see <<_timeh>> CSR)**
|
4+^| **System Time (see <<_timeh>> CSR)**
|
| `time_i` | 64 | in | system time input (from MTIME)
|
| `time_i` | 64 | in | system time input (from MTIME)
|
4+^| **Non-Maskable Interrupt (<<_traps_exceptions_and_interrupts>>)**
|
|
| `nm_irq_i` | 1 | in | non-maskable interrupt
|
|
4+^| **Interrupts, RISC-V-compatible (<<_traps_exceptions_and_interrupts>>)**
|
4+^| **Interrupts, RISC-V-compatible (<<_traps_exceptions_and_interrupts>>)**
|
| `msw_irq_i` | 1 | in | RISC-V machine software interrupt
|
| `msw_irq_i` | 1 | in | RISC-V machine software interrupt
|
| `mext_irq_i` | 1 | in | RISC-V machine external interrupt
|
| `mext_irq_i` | 1 | in | RISC-V machine external interrupt
|
| `mtime_irq_i` | 1 | in | RISC-V machine timer interrupt
|
| `mtime_irq_i` | 1 | in | RISC-V machine timer interrupt
|
4+^| **Fast Interrupts, NEORV32-specific (<<_traps_exceptions_and_interrupts>>)**
|
4+^| **Fast Interrupts, NEORV32-specific (<<_traps_exceptions_and_interrupts>>)**
|
| `firq_i` | 16 | in | fast interrupt request signals
|
| `firq_i` | 16 | in | fast interrupt request signals
|
| `firq_ack_o` | 16 | out | fast interrupt acknowledge signals
|
|
4+^| **Enter Debug Mode Request (<<_on_chip_debugger_ocd>>)**
|
4+^| **Enter Debug Mode Request (<<_on_chip_debugger_ocd>>)**
|
| `db_halt_req_i` | 1 | in | request CPU to halt and enter debug mode
|
| `db_halt_req_i` | 1 | in | request CPU to halt and enter debug mode
|
|=======================
|
|=======================
|
|
|
|
|
| Line 342... |
Line 342... |
see the The _RISC-V Instruction Set Manual – Volume I: Unprivileged ISA_ and _The RISC-V Instruction Set Manual
|
see the The _RISC-V Instruction Set Manual – Volume I: Unprivileged ISA_ and _The RISC-V Instruction Set Manual
|
Volume II: Privileged Architecture_, which are available in the projects `docs/references` folder.
|
Volume II: Privileged Architecture_, which are available in the projects `docs/references` folder.
|
|
|
[TIP]
|
[TIP]
|
The CPU can discover available ISA extensions via the <<_misa>> CSR and the
|
The CPU can discover available ISA extensions via the <<_misa>> CSR and the
|
_SYSINFO_CPU_ <<_system_configuration_information_memory_sysinfo, SYSINFO>> register
|
`CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register
|
or by executing an instruction and checking for an _illegal instruction exception_.
|
or by executing an instruction and checking for an _illegal instruction exception_.
|
|
|
[NOTE]
|
[NOTE]
|
Executing an instruction from an extension that is not implemented or not enabled (for example via the according
|
Executing an instruction from an extension that is not implemented or not enabled (for example via the according
|
top entity generic) will raise an _illegal instruction_ exception.
|
top entity generic) will raise an _illegal instruction_ exception.
|
| Line 468... |
Line 468... |
|
|
The NEORV32-specific extensions are always enabled and are indicated by the set `X` bit in the `misa` CSR.
|
The NEORV32-specific extensions are always enabled and are indicated by the set `X` bit in the `misa` CSR.
|
|
|
The most important points of the NEORV32-specific extensions are:
|
The most important points of the NEORV32-specific extensions are:
|
* The CPU provides 16 _fast interrupt_ interrupts (`FIRQ)`, which are controlled via custom bits in the `mie`
|
* The CPU provides 16 _fast interrupt_ interrupts (`FIRQ)`, which are controlled via custom bits in the `mie`
|
and `mip` CSR. This extension is mapped to bits, that are available for custom use (according to the
|
and `mip` CSR. This extension is mapped to _reserved_ CSR bits, that are available for custom use (according to the
|
RISC-V specs). Also, custom trap codes for `mcause` are implemented.
|
RISC-V specs). Also, custom trap codes for `mcause` are implemented.
|
* The CPU provides a single _non-maskable_ interrupt (`NMI)` that also provides a custom trap code for `mcause`.
|
|
* All undefined/unimplemented/malformed/illegal instructions do raise an illegal instruction exception (see <<_full_virtualization>>).
|
* All undefined/unimplemented/malformed/illegal instructions do raise an illegal instruction exception (see <<_full_virtualization>>).
|
|
|
|
|
==== **`Zfinx`** Single-Precision Floating-Point Operations
|
==== **`Zfinx`** Single-Precision Floating-Point Operations
|
|
|
| Line 580... |
Line 579... |
|
|
* `fence.i`
|
* `fence.i`
|
|
|
[NOTE]
|
[NOTE]
|
The `fence.i` instruction resets the CPU's internal instruction fetch engine and flushes the prefetch buffer.
|
The `fence.i` instruction resets the CPU's internal instruction fetch engine and flushes the prefetch buffer.
|
This allows a clean re-fetch of modified data from memory. Also, the top's `i_bus_fencei_o` signal is set
|
This allows a clean re-fetch of modified instructions from memory. Also, the top's `i_bus_fencei_o` signal is set
|
high for one cycle to inform the memory system. Any additional flags within the `fence.i` instruction word
|
high for one cycle to inform the memory system (like the i-cache to perform a flush/reload.
|
are ignore by the hardware.
|
Any additional flags within the `fence.i` instruction word are ignore by the hardware.
|
|
|
[NOTE]
|
|
If the `Zifencei` extension is disabled (_CPU_EXTENSION_RISCV_Zifencei_ generic = false) executing
|
|
a `fence.i` instruction will be executed as `nop` (and will **not trap**) and none of the functions
|
|
described above will be executed.
|
|
|
|
|
|
==== **`PMP`** Physical Memory Protection
|
==== **`PMP`** Physical Memory Protection
|
|
|
The NEORV32 physical memory protection (PMP) is compatible to the PMP specified by the RISC-V specs.
|
The NEORV32 physical memory protection (PMP) is compatible to the PMP specified by the RISC-V specs.
|
| Line 781... |
Line 775... |
:sectnums:
|
:sectnums:
|
==== Traps, Exceptions and Interrupts
|
==== Traps, Exceptions and Interrupts
|
|
|
In this document the following nomenclature regarding traps is used:
|
In this document the following nomenclature regarding traps is used:
|
|
|
* _interrupt_ = asynchronous exceptions
|
* _interrupts_ = asynchronous exceptions
|
* _exceptions_ = synchronous exceptions
|
* _exceptions_ = synchronous exceptions
|
* _traps_ = exceptions + interrupts (synchronous or asynchronous exceptions)
|
* _traps_ = exceptions + interrupts (synchronous or asynchronous exceptions)
|
|
|
Whenever an exception or interrupt is triggered, the CPU transfers control to the address stored in `mtvec`
|
Whenever an exception or interrupt is triggered, the CPU transfers control to the address stored in `mtvec`
|
CSR. The cause of the according interrupt or exception can be determined via the content of `mcause`
|
CSR. The cause of the according interrupt or exception can be determined via the content of `mcause`
|
CSR. The address that reflects the current program counter when a trap was taken is stored to `mepc` CSR.
|
CSR. The address that reflects the current program counter when a trap was taken is stored to `mepc` CSR.
|
Additional information regarding the cause of the trap can be retrieved from `mtval` CSR.
|
Additional information regarding the cause of the trap can be retrieved from `mtval` CSR.
|
|
|
The traps are prioritized. If several _exceptions_ occur at once only the one with highest priority is triggered
|
The traps are prioritized. If several _exceptions_ occur at once only the one with highest priority is triggered
|
while all remaining exceptions are ignored. If several _interrupts_ trigger at once, the one with highest priority
|
while all remaining exceptions are ignored. If several _interrupts_ trigger at once, the one with highest priority
|
is serviced first while the remaining ones are queued. After completing the interrupt handler the interrupt with
|
is serviced first while the remaining ones stay _pending_. After completing the interrupt handler the interrupt with
|
the second highest priority will get serviced and so on until no further interrupt are pending.
|
the second highest priority will get serviced and so on until no further interrupt are pending.
|
|
|
.Trigger Type
|
.RISC-V interrupts
|
[IMPORTANT]
|
[IMPORTANT]
|
All CPU interrupt request signals are high-level triggered. So an interrupt request will be generated if the
|
All RISC-V defined machine level interrupts request signals are high-active. A request has to stay at high-level until
|
according signal is _high_ for exactly one cycle (being high for several cycles might cause multiple
|
it is acknowledged by the CPU (for example by writing to a specific memory-mapped register).
|
triggering of the same interrupt).
|
|
|
|
.Instruction Atomicity
|
.Instruction Atomicity
|
[NOTE]
|
[NOTE]
|
All instructions execute as atomic operations – interrupts can only trigger between two instructions.
|
All instructions execute as atomic operations – interrupts can only trigger between two instructions.
|
|
So if there is a permanent interrupt request, exactly one instruction from the interrupt program will be executed before
|
|
a new interrupt handler can start.
|
|
|
|
|
:sectnums:
|
:sectnums:
|
==== Memory Access Exceptions**
|
==== Memory Access Exceptions**
|
|
|
If a load operation causes any exception, the instruction's destination register is
|
If a load operation causes any exception, the instruction's destination register is
|
_not written_ at all. Load exceptions caused by a misalignment or a physical memory protection fault do not
|
_not written_ at all. Load exceptions caused by a misalignment or a physical memory protection fault do not
|
trigger a bus read-operation at all. Exceptions caused by a store address misalignment or a store physical
|
trigger a bus read-operation at all. Exceptions caused by a store address misalignment or a store physical
|
memory protection fault do not trigger
|
memory protection fault do not trigger a bus write-operation at all.
|
a bus write-operation at all.
|
|
|
|
|
|
:sectnums:
|
:sectnums:
|
==== Custom Fast Interrupt Request Lines
|
==== Custom Fast Interrupt Request Lines
|
|
|
As a custom extension, the NEORV32 CPU features 16 fast interrupt request (FIRQ) lines via the `firq_i` CPU top
|
As a custom extension, the NEORV32 CPU features 16 fast interrupt request (FIRQ) lines via the `firq_i` CPU top
|
entity signals. These interrupts have custom configuration and status flags in the `mie` and `mip` CSRs and also
|
entity signals. These interrupts have custom configuration and status flags in the `mie` and `mip` CSRs and also
|
provide custom trap codes in `mcause`. Thes FIRQs are reserved for processor-internal usage only.
|
provide custom trap codes in `mcause`. These FIRQs are reserved for processor-internal usage only.
|
|
|
|
|
:sectnums:
|
|
==== Non-Maskable Interrupt
|
|
|
|
The NEORV32 CPU features a single non-maskable interrupt source via the `nm_irq_i` CPU (/Processor) top
|
|
entity signal. This interrupt can be used to signal _critical_ system conditions that need immediate handling.
|
|
The non-maskable interrupt _cannot_ be masked/disabled at all (even not in interrupt service routines).
|
|
Hence, it does _not_ provide configuration/status flags in the `mie` and `mip` CSRs. The RISC-V-compatible
|
|
`mcause` value `0x80000000` is used to indicate the non-maskable interrupt.
|
|
|
|
|
[NOTE]
|
|
The fast interrupt request lines trigger on a **rising-edge**.
|
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums!:
|
:sectnums!:
|
| Line 845... |
Line 831... |
.NEORV32 trap listing
|
.NEORV32 trap listing
|
[cols="3,6,5,14,11,4,4"]
|
[cols="3,6,5,14,11,4,4"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Prio. | `mcause` | [RISC-V] | ID [C] | Cause | `mepc` | `mtval`
|
| Prio. | `mcause` | [RISC-V] | ID [C] | Cause | `mepc` | `mtval`
|
| 1 | `0x80000000` | 1.0 | _TRAP_CODE_NMI_ | non-maskable interrupt | _I-PC_ | _0_
|
| 1 | `0x00000000` | 0.0 | _TRAP_CODE_I_MISALIGNED_ | instruction address misaligned | _B-ADR_ | _PC_
|
| 2 | `0x8000000B` | 1.11 | _TRAP_CODE_MEI_ | machine external interrupt | _I-PC_ | _0_
|
| 2 | `0x00000001` | 0.1 | _TRAP_CODE_I_ACCESS_ | instruction access fault | _B-ADR_ | _PC_
|
| 3 | `0x80000003` | 1.3 | _TRAP_CODE_MSI_ | machine software interrupt | _I-PC_ | _0_
|
| 3 | `0x00000002` | 0.2 | _TRAP_CODE_I_ILLEGAL_ | illegal instruction | _PC_ | _Inst_
|
| 4 | `0x80000007` | 1.7 | _TRAP_CODE_MTI_ | machine timer interrupt | _I-PC_ | _0_
|
| 4 | `0x0000000B` | 0.11 | _TRAP_CODE_MENV_CALL_ | environment call from M-mode (`ecall` in machine-mode) | _PC_ | _PC_
|
| 5 | `0x80000010` | 1.16 | _TRAP_CODE_FIRQ_0_ | fast interrupt request channel 0 | _I-PC_ | _0_
|
| 5 | `0x00000008` | 0.8 | _TRAP_CODE_UENV_CALL_ | environment call from U-mode (`ecall` in user-mode) | _PC_ | _PC_
|
| 6 | `0x80000011` | 1.17 | _TRAP_CODE_FIRQ_1_ | fast interrupt request channel 1 | _I-PC_ | _0_
|
| 6 | `0x00000003` | 0.3 | _TRAP_CODE_BREAKPOINT_ | breakpoint (EBREAK) | _PC_ | _PC_
|
| 7 | `0x80000012` | 1.18 | _TRAP_CODE_FIRQ_2_ | fast interrupt request channel 2 | _I-PC_ | _0_
|
| 7 | `0x00000006` | 0.6 | _TRAP_CODE_S_MISALIGNED_ | store address misaligned | _B-ADR_ | _B-ADR_
|
| 8 | `0x80000013` | 1.19 | _TRAP_CODE_FIRQ_3_ | fast interrupt request channel 3 | _I-PC_ | _0_
|
| 8 | `0x00000004` | 0.4 | _TRAP_CODE_L_MISALIGNED_ | load address misaligned | _B-ADR_ | _B-ADR_
|
| 9 | `0x80000014` | 1.20 | _TRAP_CODE_FIRQ_4_ | fast interrupt request channel 4 | _I-PC_ | _0_
|
| 9 | `0x00000007` | 0.7 | _TRAP_CODE_S_ACCESS_ | store access fault | _B-ADR_ | _B-ADR_
|
| 10 | `0x80000015` | 1.21 | _TRAP_CODE_FIRQ_5_ | fast interrupt request channel 5 | _I-PC_ | _0_
|
| 10 | `0x00000005` | 0.5 | _TRAP_CODE_L_ACCESS_ | load access fault | _B-ADR_ | _B-ADR_
|
| 11 | `0x80000016` | 1.22 | _TRAP_CODE_FIRQ_6_ | fast interrupt request channel 6 | _I-PC_ | _0_
|
| 11 | `0x80000010` | 1.16 | _TRAP_CODE_FIRQ_0_ | fast interrupt request channel 0 | _I-PC_ | _0_
|
| 12 | `0x80000017` | 1.23 | _TRAP_CODE_FIRQ_7_ | fast interrupt request channel 7 | _I-PC_ | _0_
|
| 12 | `0x80000011` | 1.17 | _TRAP_CODE_FIRQ_1_ | fast interrupt request channel 1 | _I-PC_ | _0_
|
| 13 | `0x80000018` | 1.24 | _TRAP_CODE_FIRQ_8_ | fast interrupt request channel 8 | _I-PC_ | _0_
|
| 13 | `0x80000012` | 1.18 | _TRAP_CODE_FIRQ_2_ | fast interrupt request channel 2 | _I-PC_ | _0_
|
| 14 | `0x80000019` | 1.25 | _TRAP_CODE_FIRQ_9_ | fast interrupt request channel 9 | _I-PC_ | _0_
|
| 14 | `0x80000013` | 1.19 | _TRAP_CODE_FIRQ_3_ | fast interrupt request channel 3 | _I-PC_ | _0_
|
| 15 | `0x8000001a` | 1.26 | _TRAP_CODE_FIRQ_10_ | fast interrupt request channel 10 | _I-PC_ | _0_
|
| 15 | `0x80000014` | 1.20 | _TRAP_CODE_FIRQ_4_ | fast interrupt request channel 4 | _I-PC_ | _0_
|
| 16 | `0x8000001b` | 1.27 | _TRAP_CODE_FIRQ_11_ | fast interrupt request channel 11 | _I-PC_ | _0_
|
| 16 | `0x80000015` | 1.21 | _TRAP_CODE_FIRQ_5_ | fast interrupt request channel 5 | _I-PC_ | _0_
|
| 17 | `0x8000001c` | 1.28 | _TRAP_CODE_FIRQ_12_ | fast interrupt request channel 12 | _I-PC_ | _0_
|
| 17 | `0x80000016` | 1.22 | _TRAP_CODE_FIRQ_6_ | fast interrupt request channel 6 | _I-PC_ | _0_
|
| 18 | `0x8000001d` | 1.29 | _TRAP_CODE_FIRQ_13_ | fast interrupt request channel 13 | _I-PC_ | _0_
|
| 18 | `0x80000017` | 1.23 | _TRAP_CODE_FIRQ_7_ | fast interrupt request channel 7 | _I-PC_ | _0_
|
| 19 | `0x8000001e` | 1.30 | _TRAP_CODE_FIRQ_14_ | fast interrupt request channel 14 | _I-PC_ | _0_
|
| 19 | `0x80000018` | 1.24 | _TRAP_CODE_FIRQ_8_ | fast interrupt request channel 8 | _I-PC_ | _0_
|
| 20 | `0x8000001f` | 1.31 | _TRAP_CODE_FIRQ_15_ | fast interrupt request channel 15 | _I-PC_ | _0_
|
| 20 | `0x80000019` | 1.25 | _TRAP_CODE_FIRQ_9_ | fast interrupt request channel 9 | _I-PC_ | _0_
|
| 21 | `0x00000001` | 0.1 | _TRAP_CODE_I_ACCESS_ | instruction access fault | _B-ADR_ | _PC_
|
| 21 | `0x8000001a` | 1.26 | _TRAP_CODE_FIRQ_10_ | fast interrupt request channel 10 | _I-PC_ | _0_
|
| 22 | `0x00000002` | 0.2 | _TRAP_CODE_I_ILLEGAL_ | illegal instruction | _PC_ | _Inst_
|
| 22 | `0x8000001b` | 1.27 | _TRAP_CODE_FIRQ_11_ | fast interrupt request channel 11 | _I-PC_ | _0_
|
| 23 | `0x00000000` | 0.0 | _TRAP_CODE_I_MISALIGNED_ | instruction address misaligned | _B-ADR_ | _PC_
|
| 23 | `0x8000001c` | 1.28 | _TRAP_CODE_FIRQ_12_ | fast interrupt request channel 12 | _I-PC_ | _0_
|
| 24 | `0x0000000B` | 0.11 | _TRAP_CODE_MENV_CALL_ | environment call from M-mode (ECALL in machine-mode) | _PC_ | _PC_
|
| 24 | `0x8000001d` | 1.29 | _TRAP_CODE_FIRQ_13_ | fast interrupt request channel 13 | _I-PC_ | _0_
|
| 25 | `0x00000008` | 0.8 | _TRAP_CODE_UENV_CALL_ | environment call from U-mode(ECALL in user-mode) | _PC_ | _PC_
|
| 25 | `0x8000001e` | 1.30 | _TRAP_CODE_FIRQ_14_ | fast interrupt request channel 14 | _I-PC_ | _0_
|
| 26 | `0x00000003` | 0.3 | _TRAP_CODE_BREAKPOINT_ | breakpoint (EBREAK) | _PC_ | _PC_
|
| 26 | `0x8000001f` | 1.31 | _TRAP_CODE_FIRQ_15_ | fast interrupt request channel 15 | _I-PC_ | _0_
|
| 27 | `0x00000006` | 0.6 | _TRAP_CODE_S_MISALIGNED_ | store address misaligned | _B-ADR_ | _B-ADR_
|
| 27 | `0x8000000B` | 1.11 | _TRAP_CODE_MEI_ | machine external interrupt | _I-PC_ | _0_
|
| 28 | `0x00000004` | 0.4 | _TRAP_CODE_L_MISALIGNED_ | load address misaligned | _B-ADR_ | _B-ADR_
|
| 28 | `0x80000003` | 1.3 | _TRAP_CODE_MSI_ | machine software interrupt | _I-PC_ | _0_
|
| 29 | `0x00000007` | 0.7 | _TRAP_CODE_S_ACCESS_ | store access fault | _B-ADR_ | _B-ADR_
|
| 29 | `0x80000007` | 1.7 | _TRAP_CODE_MTI_ | machine timer interrupt | _I-PC_ | _0_
|
| 30 | `0x00000005` | 0.5 | _TRAP_CODE_L_ACCESS_ | lad access fault | _B-ADR_ | _B-ADR_
|
|
|=======================
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|=======================
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**Notes**
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**Notes**
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The "Prio." column shows the priority of each trap. The highest priority is 1. The "`mcause`" column shows the
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The "Prio." column shows the priority of each trap. The highest priority is 1. The "`mcause`" column shows the
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