| Line 105... |
Line 105... |
| 0xf11 | <<_mvendorid>> | _CSR_MVENDORID_ | r/- | Vendor ID |
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| 0xf11 | <<_mvendorid>> | _CSR_MVENDORID_ | r/- | Vendor ID |
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| 0xf12 | <<_marchid>> | _CSR_MARCHID_ | r/- | Architecture ID |
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| 0xf12 | <<_marchid>> | _CSR_MARCHID_ | r/- | Architecture ID |
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| 0xf13 | <<_mimpid>> | _CSR_MIMPID_ | r/- | Machine implementation ID / version |
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| 0xf13 | <<_mimpid>> | _CSR_MIMPID_ | r/- | Machine implementation ID / version |
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| 0xf14 | <<_mhartid>> | _CSR_MHARTID_ | r/- | Machine thread ID |
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| 0xf14 | <<_mhartid>> | _CSR_MHARTID_ | r/- | Machine thread ID |
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| 0xf15 | <<_mconfigptr>> | _CSR_MCONFIGPTR_ | r/- | Machine configuration pointer register |
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| 0xf15 | <<_mconfigptr>> | _CSR_MCONFIGPTR_ | r/- | Machine configuration pointer register |
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6+^| **<<_neorv32_specific_custom_csrs>>**
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| 0xfc0 | <<_mzext>> | _CSR_MZEXT_ | r/- | Available `Z*` CPU extensions |
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|=======================
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|=======================
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| Line 186... |
Line 184... |
[options="header",grid="rows"]
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[options="header",grid="rows"]
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|=======================
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|=======================
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| Bit | Name [C] | R/W | Function
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| Bit | Name [C] | R/W | Function
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| 31 | _CSR_MSTATUS_SD_ | r/- | Read-only bit that is set if the FS field is not all-zero (state _OFF_)
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| 31 | _CSR_MSTATUS_SD_ | r/- | Read-only bit that is set if the FS field is not all-zero (state _OFF_)
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| 21 | _CSR_MSTATUS_TW_ | r/w | Timeout wait: raise illegal instruction exception if `WFI` instruction is executed outside of M-mode when set
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| 21 | _CSR_MSTATUS_TW_ | r/w | Timeout wait: raise illegal instruction exception if `WFI` instruction is executed outside of M-mode when set
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| 14:13 | _CSR_MSTATUS_FS_H_ : _CSR_MSTATUS_FS_L_ | r/w | Floating-point extension state; `00` = _OFF_, `11` = _DIRTY_; writing any other value will
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always set _DIRTY_; if `FS` is _off_ all FPU instructions and FPU CSR access will raise an illegal instruction exception; these status bits are hardwired
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to zero if no FPU is present (_CPU_MZEXT_ZFINX_ = false)
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| 12:11 | _CSR_MSTATUS_MPP_H_ : _CSR_MSTATUS_MPP_L_ | r/w | Previous machine privilege level, 11 = machine (M) level, 00 = user (U) level
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| 12:11 | _CSR_MSTATUS_MPP_H_ : _CSR_MSTATUS_MPP_L_ | r/w | Previous machine privilege level, 11 = machine (M) level, 00 = user (U) level
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| 7 | _CSR_MSTATUS_MPIE_ | r/w | Previous machine global interrupt enable flag state
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| 7 | _CSR_MSTATUS_MPIE_ | r/w | Previous machine global interrupt enable flag state
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| 3 | _CSR_MSTATUS_MIE_ | r/w | Machine global interrupt enable flag
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| 3 | _CSR_MSTATUS_MIE_ | r/w | Machine global interrupt enable flag
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|=======================
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|=======================
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| Line 231... |
Line 226... |
| 2 | _CSR_MISA_C_EXT_ | r/- | `C` CPU extension (compressed instruction) available, set when _CPU_EXTENSION_RISCV_C_ enabled
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| 2 | _CSR_MISA_C_EXT_ | r/- | `C` CPU extension (compressed instruction) available, set when _CPU_EXTENSION_RISCV_C_ enabled
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| 0 | _CSR_MISA_A_EXT_ | r/- | `A` CPU extension (atomic memory access) available, set when _CPU_EXTENSION_RISCV_A_ enabled
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| 0 | _CSR_MISA_A_EXT_ | r/- | `A` CPU extension (atomic memory access) available, set when _CPU_EXTENSION_RISCV_A_ enabled
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|=======================
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|=======================
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[TIP]
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[TIP]
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Information regarding the implemented RISC-V `Z*` _sub-extensions_ (like `Zicsr` or `Zfinx`) can be found in the <<_mzext>> CSR.
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Information regarding the implemented RISC-V `Z*` _sub-extensions_ (like `Zicsr` or `Zfinx`) can be found
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in the _SYSINFO_CPU_ <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
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:sectnums!:
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:sectnums!:
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===== **`mie`**
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===== **`mie`**
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| Line 510... |
Line 506... |
configuration with <<_cpu_cnt_width>> less than 64 is not RISC-V compliant.
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configuration with <<_cpu_cnt_width>> less than 64 is not RISC-V compliant.
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[IMPORTANT]
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[IMPORTANT]
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If _CPU_CNT_WIDTH_ is less than 64 (the default value) and greater than or equal 32, the according
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If _CPU_CNT_WIDTH_ is less than 64 (the default value) and greater than or equal 32, the according
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MSBs of `[m]cycleh` and `[m]instreth` are read-only and always read as zero. This configuration
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MSBs of `[m]cycleh` and `[m]instreth` are read-only and always read as zero. This configuration
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will also set the _ZXSCNT_ flag in the <<_mzext>> CSR. +
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will also set the _SYSINFO_CPU_ZXSCNT_ flag in the _SYSINFO_CPU_ <<_system_configuration_information_memory_sysinfo, SYSINFO>> register. +
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+
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+
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If _CPU_CNT_WIDTH_ is less than 32 and greater than 0, the `[m]cycleh` and `[m]instreth` do not
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If _CPU_CNT_WIDTH_ is less than 32 and greater than 0, the `[m]cycleh` and `[m]instreth` do not
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exist and any access will raise an illegal instruction exception. Furthermore, the according MSBs of
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exist and any access will raise an illegal instruction exception. Furthermore, the according MSBs of
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`[m]cycle` and `[m]instret` are read-only and always read as zero. This configuration will also
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`[m]cycle` and `[m]instret` are read-only and always read as zero. This configuration will also
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set the _ZXSCNT_ flag in the <<_mzext>> CSR. +
|
set the _SYSINFO_CPU_ZXSCNT_ flag in the _SYSINFO_CPU_ <<_system_configuration_information_memory_sysinfo, SYSINFO>> register. +
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+
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+
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If _CPU_CNT_WIDTH_ is 0, <<_cycleh>> and <<_instreth>> / <<_mcycleh>> and <<_minstreth>> do not
|
If _CPU_CNT_WIDTH_ is 0, <<_cycleh>> and <<_instreth>> / <<_mcycleh>> and <<_minstreth>> do not
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exist and any access will raise an illegal instruction exception. This configuration will also set the
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exist and any access will raise an illegal instruction exception. This configuration will also set the
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_ZXNOCNT_ flag in the <<_mzext>> CSR.
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_SYSINFO_CPU_ZXNOCNT_ flag in the _SYSINFO_CPU_ <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
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:sectnums!:
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:sectnums!:
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===== **`cycle[h]`**
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===== **`cycle[h]`**
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| Line 780... |
Line 776... |
3+| Reset value: `0x00000000`
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3+| Reset value: `0x00000000`
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3+| This register holds a physical address (if not zero) that points to the base address of an architecture configuration structure.
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3+| This register holds a physical address (if not zero) that points to the base address of an architecture configuration structure.
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Software can traverse this data structure to discover information about the harts, the platform, and their configuration.
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Software can traverse this data structure to discover information about the harts, the platform, and their configuration.
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**NOTE: Not assigned yet.**
|
**NOTE: Not assigned yet.**
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|======
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|======
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// ####################################################################################################################
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:sectnums:
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==== NEORV32-Specific Custom CSRs
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:sectnums!:
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===== **`mzext`**
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[cols="4,27,>7"]
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[frame="topbot",grid="none"]
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|======
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| 0xfc0 | **Available Z* extensions** | `mzext`
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3+| Reset value: _0x00000000_
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3+| The `mzext` CSR is a custom read-only CSR that shows the implemented Z* extensions. The following bits
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are implemented (all remaining bits are always zero). The entire CSR is read-only.
|
|
|======
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|
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.Machine counter-inhibit register
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[cols="^1,<3,^1,<5"]
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[options="header",grid="rows"]
|
|
|=======================
|
|
| Bit | Name [C] | R/W | Event
|
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| 0 | _CPU_MZEXT_ZICSR_ | r/- | `Zicsr` extensions available (enabled via <<_cpu_extension_riscv_zicsr>> generic)
|
|
| 1 | _CPU_MZEXT_ZIFENCEI_ | r/- | `Zifencei` extensions available (enabled via <<_cpu_extension_riscv_zifencei>> generic)
|
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| 2 | _CPU_MZEXT_ZMMUL_ | r/- | `Zmmul` extensions available (enabled via <<_cpu_extension_riscv_zmmul>> generic)
|
|
| 5 | _CPU_MZEXT_ZFINX_ | r/- | `Zfinx` extensions available (enabled via <<_cpu_extension_riscv_zfinx>> generic)
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|
| 6 | _CPU_MZEXT_ZXSCNT_ | r/- | custom extension: "Small CPU counters": `cycle[h]` & `instret[h]` CSRs have less than 64-bit when set (when <<_cpu_cnt_width>> generic is less than 64)
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| 7 | _CPU_MZEXT_ZXNOCNT_ | r/- | custom extension: "NO CPU counters": `cycle[h]` & `instret[h]` CSRs are not available at all when set (when <<_cpu_cnt_width>> generic is 0)
|
|
| 8 | _CSR_MZEXT_PMP_ | r/- | PMP (physical memory protection) extension available (<<_pmp_num_regions>> generic > 0)
|
|
| 9 | _CSR_MZEXT_HPM_ | r/- | HPM (hardware performance monitors) extension available (<<_hpm_num_cnts>> generic > 0)
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| 10 | _CSR_MZEXT_DEBUGMODE_ | r/- | RISC-V "CPU debug mode" extension available (enabled via <<_cpu_top_entity_generics,_CPU_EXTENSION_RISCV_DEBUG_>> generic)
|
|
|=======================
|
|
