| Line 216... |
Line 216... |
.Machine status register
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.Machine status register
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[cols="^1,<3,^1,<5"]
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[cols="^1,<3,^1,<5"]
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[options="header",grid="rows"]
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[options="header",grid="rows"]
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|=======================
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|=======================
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| Bit | Name [C] | R/W | Function
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| Bit | Name [C] | R/W | Function
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| 21 | _CSR_MSTATUS_TW_ | r/w | Timeout wait: raise illegal instruction exception if `WFI` instruction is executed outside of M-mode when set
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| 12:11 | _CSR_MSTATUS_MPP_H_ : _CSR_MSTATUS_MPP_L_ | r/w | Previous machine privilege level, 11 = machine (M) level, 00 = user (U) level
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| 12:11 | _CSR_MSTATUS_MPP_H_ : _CSR_MSTATUS_MPP_L_ | r/w | Previous machine privilege level, 11 = machine (M) level, 00 = user (U) level
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| 7 | _CSR_MSTATUS_MPIE_ | r/w | Previous machine global interrupt enable flag state
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| 7 | _CSR_MSTATUS_MPIE_ | r/w | Previous machine global interrupt enable flag state
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| 3 | _CSR_MSTATUS_MIE_ | r/w | Machine global interrupt enable flag
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| 3 | _CSR_MSTATUS_MIE_ | r/w | Machine global interrupt enable flag
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|=======================
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|=======================
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| Line 444... |
Line 443... |
[cols="4,27,>7"]
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[cols="4,27,>7"]
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[frame="topbot",grid="none"]
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[frame="topbot",grid="none"]
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|======
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|======
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| 0x344 | **Machine interrupt Pending** | `mip`
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| 0x344 | **Machine interrupt Pending** | `mip`
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3+| Reset value: _0x00000000_
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3+| Reset value: _0x00000000_
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3+| The `mip` CSR is _partly_ compatible to the RISC-V specifications and also provides custom extensions. It shows currently pending interrupts. Since this register is
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3+| The `mip` CSR is compatible to the RISC-V specifications and also provides custom extensions. It shows currently _pending_ interrupts.
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read-only, pending interrupts of processor-internal modules can only be cleared by disabling and re-enabling the according `mie` CSR bit.
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Since this register is read-only, pending interrupts of processor-internal modules can only be cleared by acknowledging the interrupt-causing
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device. However, pending interrupts can be ignored by clearing the accordind <<_mie>> register bits.
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The following CSR bits are implemented (all remaining bits are always zero and are read-only).
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The following CSR bits are implemented (all remaining bits are always zero and are read-only).
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|======
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|======
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.Machine interrupt pending register
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.Machine interrupt pending register
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[cols="^1,<3,^1,<5"]
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[cols="^1,<3,^1,<5"]
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| Line 500... |
Line 500... |
.Physical memory protection configuration register entry
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.Physical memory protection configuration register entry
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[cols="^1,^3,^1,<11"]
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[cols="^1,^3,^1,<11"]
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[options="header",grid="rows"]
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[options="header",grid="rows"]
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|=======================
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|=======================
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| Bit | RISC-V name | R/W | Function
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| Bit | RISC-V name | R/W | Function
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| 7 | _L_ | r/w | lock bit, can be set – but not be cleared again (only via CPU reset)
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| 7 | _L_ | r/w | lock bit, can be set - but not be cleared again (only via CPU reset)
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| 6:5 | - | r/- | reserved, read as zero
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| 6:5 | - | r/- | reserved, read as zero
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| 4:3 | _A_ | r/w | mode configuration; only OFF (`00`) and NAPOT (`11`) are supported
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| 4:3 | _A_ | r/w | mode configuration; only OFF (`00`) and NAPOT (`11`) are supported
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| 2 | _X_ | r/w | execute permission
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| 2 | _X_ | r/w | execute permission
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| 1 | _W_ | r/w | write permission
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| 1 | _W_ | r/w | write permission
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| 0 | _R_ | r/w | read permission
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| 0 | _R_ | r/w | read permission
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