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│├references - Data sheets and RISC-V specs.
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│├references - Data sheets and RISC-V specs.
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│└src_adoc - AsciiDoc sources for this document
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│└src_adoc - AsciiDoc sources for this document
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│
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│
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├rtl - VHDL sources
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├rtl - VHDL sources
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│├core - Core sources of the CPU & SoC
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│├core - Core sources of the CPU & SoC
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│└templates - Alternate/additional top entities & wrappers
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│├processor_templates - Pre-configured SoC wrappers
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│ ├processor - Processor SoC wrappers
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│├system_integration - System wrappers for advanced connectivity
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│ └system - System wrappers for advanced connectivity
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│└test_setups - Minimal test setup "SoCs" used in the User Guide
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│
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│
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├setups - Example setups for various FPGAs, boards and toolchains
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├setups - Example setups for various FPGAs, boards and toolchains
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│└...
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│└...
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│
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│
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├sim - Simulation files (see User Guide)
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├sim - Simulation files (see User Guide)
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├neorv32_fifo.vhd - General purpose FIFO component
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├neorv32_fifo.vhd - General purpose FIFO component
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├neorv32_package.vhd - Processor/CPU main VHDL package file
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├neorv32_package.vhd - Processor/CPU main VHDL package file
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│
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│
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├neorv32_cpu.vhd - NEORV32 CPU top entity
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├neorv32_cpu.vhd - NEORV32 CPU top entity
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│├neorv32_cpu_alu.vhd - Arithmetic/logic unit
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│├neorv32_cpu_alu.vhd - Arithmetic/logic unit
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││├neorv32_cpu_cp_bitmanip.vhd - Bit-manipulation co-processor (B ext.)
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││├neorv32_cpu_cp_fpu.vhd - Floating-point co-processor (Zfinx ext.)
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││├neorv32_cpu_cp_fpu.vhd - Floating-point co-processor (Zfinx ext.)
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││├neorv32_cpu_cp_muldiv.vhd - Mul/Div co-processor (M extension)
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││├neorv32_cpu_cp_muldiv.vhd - Mul/Div co-processor (M extension)
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││└neorv32_cpu_cp_shifter.vhd - Bit-shift co-processor
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││└neorv32_cpu_cp_shifter.vhd - Bit-shift co-processor
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│├neorv32_cpu_bus.vhd - Bus interface + physical memory protection
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│├neorv32_cpu_bus.vhd - Bus interface + physical memory protection
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│├neorv32_cpu_control.vhd - CPU control, exception/IRQ system and CSRs
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│├neorv32_cpu_control.vhd - CPU control, exception/IRQ system and CSRs
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No HPM counters and no PMP regions were implemented for generating these results.
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No HPM counters and no PMP regions were implemented for generating these results.
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[TIP]
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[TIP]
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The CPU provides further options to reduce the area footprint (for example by constraining the CPU-internal
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The CPU provides further options to reduce the area footprint (for example by constraining the CPU-internal
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counter sizes) or to increase performance (for example by using a barrel-shifter; at cost of extra hardware).
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counter sizes) or to increase performance (for example by using a barrel-shifter; at cost of extra hardware).
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See section <<_processor_top_entity_generics>> for more information.
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See section <<_processor_top_entity_generics>> for more information. Also, take a look at the User Guide section
|
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https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration[Application-Specific Processor Configuration].
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:sectnums:
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:sectnums:
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==== Processor Modules
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==== Processor Modules
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The performance of the NEORV32 was tested and evaluated using the https://www.eembc.org/coremark/[Core Mark CPU benchmark].
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The performance of the NEORV32 was tested and evaluated using the https://www.eembc.org/coremark/[Core Mark CPU benchmark].
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This benchmark focuses on testing the capabilities of the CPU core itself rather than the performance of the whole
|
This benchmark focuses on testing the capabilities of the CPU core itself rather than the performance of the whole
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system. The according sources can be found in the `sw/example/coremark` folder.
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system. The according sources can be found in the `sw/example/coremark` folder.
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.Dhrystone
|
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[TIP]
|
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A _simple_ port of the Dhrystone benchmark is also available in `sw/example/dhrystone`.
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|
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The resulting CoreMark score is defined as CoreMark iterations per second.
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The resulting CoreMark score is defined as CoreMark iterations per second.
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The execution time is determined via the RISC-V `[m]cycle[h]` CSRs. The relative CoreMark score is
|
The execution time is determined via the RISC-V `[m]cycle[h]` CSRs. The relative CoreMark score is
|
defined as CoreMark score divided by the CPU's clock frequency in MHz.
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defined as CoreMark score divided by the CPU's clock frequency in MHz.
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.Configuration
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.Configuration
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