| Line 179... |
Line 179... |
└sw - Software framework
|
└sw - Software framework
|
├bootloader - Sources of the processor-internal bootloader
|
├bootloader - Sources of the processor-internal bootloader
|
├common - Linker script, crt0.S start-up code and central makefile
|
├common - Linker script, crt0.S start-up code and central makefile
|
├example - Various example programs
|
├example - Various example programs
|
│└...
|
│└...
|
|
├lib - Processor core library
|
|
│├include - Header files (*.h)
|
|
│└source - Source files (*.c)
|
|
├image_gen - Helper program to generate NEORV32 executables
|
├isa-test
|
├isa-test
|
│├riscv-arch-test - RISC-V spec. compatibility test framework (submodule)
|
│├riscv-arch-test - RISC-V spec. compatibility test framework (submodule)
|
│└port-neorv32 - Port files for the official RISC-V architecture tests
|
│└port-neorv32 - Port files for the official RISC-V architecture tests
|
├ocd_firmware - Source code for on-chip debugger's "park loop"
|
├ocd_firmware - Source code for on-chip debugger's "park loop"
|
├openocd - OpenOCD on-chip debugger configuration files
|
├openocd - OpenOCD on-chip debugger configuration files
|
├image_gen - Helper program to generate NEORV32 executables
|
└svd - Processor system view description file (CMSIS-SVD)
|
└lib - Processor core library
|
|
├include - Header files (*.h)
|
|
└source - Source files (*.c)
|
|
...................................
|
...................................
|
|
|
|
|
|
|
|
|
| Line 275... |
Line 276... |
[cols="<2,<8"]
|
[cols="<2,<8"]
|
[grid="topbot"]
|
[grid="topbot"]
|
|=======================
|
|=======================
|
| Hardware version: | `1.5.7.10`
|
| Hardware version: | `1.5.7.10`
|
| Top entity: | `rtl/core/neorv32_cpu.vhd`
|
| Top entity: | `rtl/core/neorv32_cpu.vhd`
|
|
| FPGA: | Intel Cyclone IV E `EP4CE22F17C6`
|
|
| Toolchain: | Quartus Prime 20.1.0
|
|=======================
|
|=======================
|
|
|
[cols="<5,>1,>1,>1,>1,>1"]
|
[cols="<5,>1,>1,>1,>1,>1"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Line 292... |
Line 295... |
| `rv32imacu_Zicsr_Zicntr_Zifencei` | 2522 | 1079 | 1024 | 0 | 122 MHz
|
| `rv32imacu_Zicsr_Zicntr_Zifencei` | 2522 | 1079 | 1024 | 0 | 122 MHz
|
| `rv32imacu_Zicsr_Zicntr_Zifencei_Zfinx` | 3807 | 1731 | 1024 | 7 | 116 MHz
|
| `rv32imacu_Zicsr_Zicntr_Zifencei_Zfinx` | 3807 | 1731 | 1024 | 7 | 116 MHz
|
| `rv32imacu_Zicsr_Zicntr_Zifencei_Zfinx_DebugMode` | 3974 | 1815 | 1024 | 7 | 116 MHz
|
| `rv32imacu_Zicsr_Zicntr_Zifencei_Zfinx_DebugMode` | 3974 | 1815 | 1024 | 7 | 116 MHz
|
|=======================
|
|=======================
|
|
|
[NOTE]
|
|
No HPM counters and no PMP regions were implemented for generating these results.
|
|
|
|
[TIP]
|
[TIP]
|
The CPU provides further options to reduce the area footprint (for example by constraining the CPU-internal
|
The CPU provides further options to reduce the area footprint (for example by constraining the CPU-internal
|
counter sizes) or to increase performance (for example by using a barrel-shifter; at cost of extra hardware).
|
counter sizes) or to increase performance (for example by using a barrel-shifter; at cost of extra hardware).
|
See section <<_processor_top_entity_generics>> for more information. Also, take a look at the User Guide section
|
See section <<_processor_top_entity_generics>> for more information. Also, take a look at the User Guide section
|
https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration[Application-Specific Processor Configuration].
|
https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration[Application-Specific Processor Configuration].
|
| Line 310... |
Line 310... |
[cols="<2,<8"]
|
[cols="<2,<8"]
|
[grid="topbot"]
|
[grid="topbot"]
|
|=======================
|
|=======================
|
| Hardware version: | `1.5.7.15`
|
| Hardware version: | `1.5.7.15`
|
| Top entity: | `rtl/core/neorv32_top.vhd`
|
| Top entity: | `rtl/core/neorv32_top.vhd`
|
|
| FPGA: | Intel Cyclone IV E `EP4CE22F17C6`
|
|
| Toolchain: | Quartus Prime 20.1.0
|
|=======================
|
|=======================
|
|
|
.Hardware utilization by the processor modules (mandatory core modules in **bold**)
|
.Hardware utilization by the processor modules (mandatory core modules in **bold**)
|
[cols="<2,<8,>1,>1,>2,>1"]
|
[cols="<2,<8,>1,>1,>2,>1"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
