| Line 14... |
Line 14... |
* _optional_ internal bootloader (<<_bootloader_rom_bootrom,**BOOTROM**>>) with UART console & SPI flash boot option
|
* _optional_ internal bootloader (<<_bootloader_rom_bootrom,**BOOTROM**>>) with UART console & SPI flash boot option
|
* _optional_ machine system timer (<<_machine_system_timer_mtime,**MTIME**>>), RISC-V-compatible
|
* _optional_ machine system timer (<<_machine_system_timer_mtime,**MTIME**>>), RISC-V-compatible
|
* _optional_ two independent universal asynchronous receivers and transmitters (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,**UART0**>>, <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,**UART1**>>) with optional hardware flow control (RTS/CTS)
|
* _optional_ two independent universal asynchronous receivers and transmitters (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,**UART0**>>, <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,**UART1**>>) with optional hardware flow control (RTS/CTS)
|
* _optional_ 8/16/24/32-bit serial peripheral interface controller (<<_serial_peripheral_interface_controller_spi,**SPI**>>) with 8 dedicated CS lines
|
* _optional_ 8/16/24/32-bit serial peripheral interface controller (<<_serial_peripheral_interface_controller_spi,**SPI**>>) with 8 dedicated CS lines
|
* _optional_ two wire serial interface controller (<<_two_wire_serial_interface_controller_twi,**TWI**>>), compatible to the I²C standard
|
* _optional_ two wire serial interface controller (<<_two_wire_serial_interface_controller_twi,**TWI**>>), compatible to the I²C standard
|
* _optional_ general purpose parallel IO port (<<_general_purpose_input_and_output_port_gpio,**GPIO**>>), 32xOut, 32xIn
|
* _optional_ general purpose parallel IO port (<<_general_purpose_input_and_output_port_gpio,**GPIO**>>), 64xOut, 64xIn
|
* _optional_ 32-bit external bus interface, Wishbone b4 / AXI4-Lite compatible (<<_processor_external_memory_interface_wishbone_axi4_lite,**WISHBONE**>>)
|
* _optional_ 32-bit external bus interface, Wishbone b4 / AXI4-Lite compatible (<<_processor_external_memory_interface_wishbone_axi4_lite,**WISHBONE**>>)
|
|
* _optional_ 32-bit stream link interface with up to 8 independent links, AXI4-Stream compatible (<<_stream_link_interface_slink,**SLINK**>>)
|
* _optional_ watchdog timer (<<_watchdog_timer_wdt,**WDT**>>)
|
* _optional_ watchdog timer (<<_watchdog_timer_wdt,**WDT**>>)
|
* _optional_ PWM controller with up to 60 channels & 8-bit duty cycle resolution (<<_pulse_width_modulation_controller_pwm,**PWM**>>)
|
* _optional_ PWM controller with up to 60 channels & 8-bit duty cycle resolution (<<_pulse_width_modulation_controller_pwm,**PWM**>>)
|
* _optional_ ring-oscillator-based true random number generator (<<_true_random_number_generator_trng,**TRNG**>>)
|
* _optional_ ring-oscillator-based true random number generator (<<_true_random_number_generator_trng,**TRNG**>>)
|
* _optional_ custom functions subsystem for custom co-processor extensions (<<_custom_functions_subsystem_cfs,**CFS**>>)
|
* _optional_ custom functions subsystem for custom co-processor extensions (<<_custom_functions_subsystem_cfs,**CFS**>>)
|
* _optional_ numerically-controlled oscillator (<<_numerically_controlled_oscillator_nco,**NCO**>>) with 3 independent channels
|
|
* _optional_ NeoPixel(TM)/WS2812-compatible smart LED interface (<<_smart_led_interface_neoled,**NEOLED**>>)
|
* _optional_ NeoPixel(TM)/WS2812-compatible smart LED interface (<<_smart_led_interface_neoled,**NEOLED**>>)
|
|
* _optional_ external interrupt controller with up to 32 channels (<<_external_interrupt_controller_xirq,**XIRQ**>>)
|
* _optional_ on-chip debugger with JTAG TAP (<<_on_chip_debugger_ocd,**OCD**>>)
|
* _optional_ on-chip debugger with JTAG TAP (<<_on_chip_debugger_ocd,**OCD**>>)
|
* system configuration information memory to check HW configuration via software (<<_system_configuration_information_memory_sysinfo,**SYSINFO**>>)
|
* system configuration information memory to check HW configuration via software (<<_system_configuration_information_memory_sysinfo,**SYSINFO**>>)
|
|
|
|
|
|
|
| Line 36... |
Line 37... |
The following table shows all interface ports of the processor top entity (`rtl/core/neorv32_top.vhd`).
|
The following table shows all interface ports of the processor top entity (`rtl/core/neorv32_top.vhd`).
|
The type of all signals is _std_ulogic_ or _std_ulogic_vector_, respectively.
|
The type of all signals is _std_ulogic_ or _std_ulogic_vector_, respectively.
|
|
|
[TIP]
|
[TIP]
|
A wrapper for the NEORV32 Processor setup providing resolved port signals can be found in
|
A wrapper for the NEORV32 Processor setup providing resolved port signals can be found in
|
`rtl/top_templates/neorv32_top_stdlogic.vhd`.
|
`rtl/templates/processor/neorv32_ProcessorTop_stdlogic.vhd`.
|
|
|
[cols="<3,^2,^2,<11"]
|
[cols="<3,^2,^2,<11"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Signal | Width | Dir. | Function
|
| Signal | Width | Dir. | Function
|
| Line 66... |
Line 67... |
| `wb_ack_i` | 1 | in | transfer acknowledge
|
| `wb_ack_i` | 1 | in | transfer acknowledge
|
| `wb_err_i` | 1 | in | transfer error
|
| `wb_err_i` | 1 | in | transfer error
|
4+^| **Advanced Memory Control Signals**
|
4+^| **Advanced Memory Control Signals**
|
| `fence_o` | 1 | out | indicates an executed _fence_ instruction
|
| `fence_o` | 1 | out | indicates an executed _fence_ instruction
|
| `fencei_o` | 1 | out | indicates an executed _fencei_ instruction
|
| `fencei_o` | 1 | out | indicates an executed _fencei_ instruction
|
|
4+^| **Stream Link Interface (<<_stream_link_interface_slink,SLINK>>)**
|
|
| `slink_tx_dat_o` | 8x32 | out | TX link _n_ data
|
|
| `slink_tx_val_o` | 8 | out | TX link _n_ data valid
|
|
| `slink_tx_rdy_i` | 8 | in | TX link _n_ allowed to send
|
|
| `slink_rx_dat_i` | 8x32 | in | RX link _n_ data
|
|
| `slink_rx_val_i` | 8 | in | RX link _n_ data valid
|
|
| `slink_rx_rdy_o` | 8 | out | RX link _n_ ready to receive
|
4+^| **General Purpose Inputs & Outputs (<<_general_purpose_input_and_output_port_gpio,GPIO>>)**
|
4+^| **General Purpose Inputs & Outputs (<<_general_purpose_input_and_output_port_gpio,GPIO>>)**
|
| `gpio_o` | 32 | out | general purpose parallel output
|
| `gpio_o` | 64 | out | general purpose parallel output
|
| `gpio_i` | 32 | in | general purpose parallel input
|
| `gpio_i` | 64 | in | general purpose parallel input
|
4+^| **Primary Universal Asynchronous Receiver/Transmitter (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>>)**
|
4+^| **Primary Universal Asynchronous Receiver/Transmitter (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>>)**
|
| `uart0_txd_o` | 1 | out | UART0 serial transmitter
|
| `uart0_txd_o` | 1 | out | UART0 serial transmitter
|
| `uart0_rxd_i` | 1 | in | UART0 serial receiver
|
| `uart0_rxd_i` | 1 | in | UART0 serial receiver
|
| `uart0_rts_o` | 1 | out | UART0 RX ready to receive new char
|
| `uart0_rts_o` | 1 | out | UART0 RX ready to receive new char
|
| `uart0_cts_i` | 1 | in | UART0 TX allowed to start sending
|
| `uart0_cts_i` | 1 | in | UART0 TX allowed to start sending
|
| Line 92... |
Line 100... |
4+^| **Custom Functions Subsystem (<<_custom_functions_subsystem_cfs,CFS>>)**
|
4+^| **Custom Functions Subsystem (<<_custom_functions_subsystem_cfs,CFS>>)**
|
| `cfs_in_i` | 32 | in | custom CFS input signal conduit
|
| `cfs_in_i` | 32 | in | custom CFS input signal conduit
|
| `cfs_out_o` | 32 | out | custom CFS output signal conduit
|
| `cfs_out_o` | 32 | out | custom CFS output signal conduit
|
4+^| **Pulse-Width Modulation Channels (<<_pulse_width_modulation_controller_pwm,PWM>>)**
|
4+^| **Pulse-Width Modulation Channels (<<_pulse_width_modulation_controller_pwm,PWM>>)**
|
| `pwm_o` | 4 | out | pulse-width modulated channels
|
| `pwm_o` | 4 | out | pulse-width modulated channels
|
4+^| **Numerically-Controller Oscillator (<<_numerically_controlled_oscillator_nco,NCO>>)**
|
|
| `nco_o` | 3 | out | NCO output channels
|
|
4+^| **Smart LED Interface - NeoPixel(TM) compatible (<<_smart_led_interface_neoled,NEOLED>>)**
|
4+^| **Smart LED Interface - NeoPixel(TM) compatible (<<_smart_led_interface_neoled,NEOLED>>)**
|
| `neoled_o` | 1 | out | asynchronous serial data output
|
| `neoled_o` | 1 | out | asynchronous serial data output
|
4+^| **System time (<<_machine_system_timer_mtime,MTIME>>)**
|
4+^| **System time (<<_machine_system_timer_mtime,MTIME>>)**
|
| `mtime_i` | 64 | in | machine timer time (to `time[h]` CSRs) from _external MTIME_ unit if the processor-internal _MTIME_ unit is NOT implemented
|
| `mtime_i` | 64 | in | machine timer time (to `time[h]` CSRs) from _external MTIME_ unit if the processor-internal _MTIME_ unit is NOT implemented
|
| `mtime_o` | 64 | out | machine timer time from _internal MTIME_ unit if processor-internal _MTIME_ unit IS implemented
|
| `mtime_o` | 64 | out | machine timer time from _internal MTIME_ unit if processor-internal _MTIME_ unit IS implemented
|
4+^| **<<_processor_interrupts>>**
|
4+^| **<<_processor_interrupts, External Interrupts>>**
|
|
| `xirq_i` | 32 | in | external interrupt requests (up to 32 channels)
|
|
4+^| **<<_processor_interrupts, CPU Interrupts>>**
|
| `nm_irq_i` | 1 | in | non-maskable interrupt
|
| `nm_irq_i` | 1 | in | non-maskable interrupt
|
| `soc_firq_i` | 6 | in | platform fast interrupt channels (custom)
|
|
| `mtime_irq_i` | 1 | in | machine timer interrupt13 (RISC-V)
|
| `mtime_irq_i` | 1 | in | machine timer interrupt13 (RISC-V)
|
| `msw_irq_i` | 1 | in | machine software interrupt (RISC-V)
|
| `msw_irq_i` | 1 | in | machine software interrupt (RISC-V)
|
| `mext_irq_i` | 1 | in | machine external interrupt (RISC-V)
|
| `mext_irq_i` | 1 | in | machine external interrupt (RISC-V)
|
|=======================
|
|=======================
|
|
|
| Line 131... |
Line 138... |
|
|
[TIP]
|
[TIP]
|
If optional modules (like CPU extensions or peripheral devices) are *not enabled* the according circuitry **will not be synthesized at all**.
|
If optional modules (like CPU extensions or peripheral devices) are *not enabled* the according circuitry **will not be synthesized at all**.
|
Hence, the disabled modules do not increase area and power requirements and do not impact the timing.
|
Hence, the disabled modules do not increase area and power requirements and do not impact the timing.
|
|
|
**CSR Description**
|
[TIP]
|
|
Not all configuration combinations are valid. The processor RTL code provides sanity checks to inform the user
|
|
during synthesis/simulation if an invalid combination has been detected.
|
|
|
|
**Generic Description**
|
|
|
The description of each CSR provides the following summary:
|
The description of each generic provides the following summary:
|
|
|
.Generic description
|
.Generic description
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| _Generic_ | _type_ | _default value_
|
| _Generic name_ | _type_ | _default value_
|
3+| _Description_
|
3+| _Description_
|
|======
|
|======
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
| Line 162... |
Line 173... |
3+| The clock frequency of the processor's `clk_i` input port in Hertz (Hz).
|
3+| The clock frequency of the processor's `clk_i` input port in Hertz (Hz).
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _BOOTLOADER_EN_
|
===== _INT_BOOTLOADER_EN_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **BOOTLOADER_EN** | _boolean_ | true
|
| **INT_BOOTLOADER_EN** | _boolean_ | true
|
3+| Implement the boot ROM, pre-initialized with the bootloader image when true. This will also change the
|
3+| Implement the processor-internal boot ROM, pre-initialized with the default bootloader image when _true_.
|
processor's boot address from the beginning of the instruction memory address space (default =
|
This will also change the processor's boot address from the beginning of the instruction memory address space (default =
|
0x00000000) to the base address of the boot ROM. See section <<_bootloader>> for more information.
|
0x00000000) to the base address of the boot ROM. See section <<_boot_configuration>> for more information.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _USER_CODE_
|
===== _USER_CODE_
|
| Line 222... |
Line 233... |
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **CPU_EXTENSION_RISCV_A** | _boolean_ | false
|
| **CPU_EXTENSION_RISCV_A** | _boolean_ | false
|
3+| Implement atomic memory access operations when _true_.
|
3+| Implement atomic memory access operations when _true_.
|
|
See section <<_a_atomic_memory_access>>.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _CPU_EXTENSION_RISCV_C_
|
===== _CPU_EXTENSION_RISCV_C_
|
| Line 233... |
Line 245... |
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **CPU_EXTENSION_RISCV_C** | _boolean_ | false
|
| **CPU_EXTENSION_RISCV_C** | _boolean_ | false
|
3+| Implement compressed instructions (16-bit) when _true_.
|
3+| Implement compressed instructions (16-bit) when _true_.
|
|
See section <<_c_compressed_instructions>>.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _CPU_EXTENSION_RISCV_E_
|
===== _CPU_EXTENSION_RISCV_E_
|
| Line 244... |
Line 257... |
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **CPU_EXTENSION_RISCV_E** | _boolean_ | false
|
| **CPU_EXTENSION_RISCV_E** | _boolean_ | false
|
3+| Implement the embedded CPU extension (only implement the first 16 data registers) when _true_.
|
3+| Implement the embedded CPU extension (only implement the first 16 data registers) when _true_.
|
|
See section <<_e_embedded_cpu>>.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _CPU_EXTENSION_RISCV_M_
|
===== _CPU_EXTENSION_RISCV_M_
|
| Line 255... |
Line 269... |
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **CPU_EXTENSION_RISCV_M** | _boolean_ | false
|
| **CPU_EXTENSION_RISCV_M** | _boolean_ | false
|
3+| Implement integer multiplication and division instructions when _true_.
|
3+| Implement integer multiplication and division instructions when _true_.
|
|
See section <<_m_integer_multiplication_and_division>>.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _CPU_EXTENSION_RISCV_U_
|
===== _CPU_EXTENSION_RISCV_U_
|
| Line 266... |
Line 281... |
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **CPU_EXTENSION_RISCV_U** | _boolean_ | false
|
| **CPU_EXTENSION_RISCV_U** | _boolean_ | false
|
3+| Implement less-privileged user mode when _true_.
|
3+| Implement less-privileged user mode when _true_.
|
|
See section <<_u_less_privileged_user_mode>>.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _CPU_EXTENSION_RISCV_Zfinx_
|
===== _CPU_EXTENSION_RISCV_Zfinx_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **CPU_EXTENSION_RISCV_Zfinx** | _boolean_ | false
|
| **CPU_EXTENSION_RISCV_Zfinx** | _boolean_ | false
|
3+| Implement the 32-bit single-precision floating-point extension (using integer registers) when _true_. For
|
3+| Implement the 32-bit single-precision floating-point extension (using integer registers) when _true_.
|
more information see section <<_zfinx_single_precision_floating_point_operations>>.
|
See section <<_zfinx_single_precision_floating_point_operations>>.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _CPU_EXTENSION_RISCV_Zicsr_
|
===== _CPU_EXTENSION_RISCV_Zicsr_
|
| Line 291... |
Line 307... |
|======
|
|======
|
| **CPU_EXTENSION_RISCV_Zicsr** | _boolean_ | true
|
| **CPU_EXTENSION_RISCV_Zicsr** | _boolean_ | true
|
3+| Implement the control and status register (CSR) access instructions when true. Note: When this option is
|
3+| Implement the control and status register (CSR) access instructions when true. Note: When this option is
|
disabled, the complete privileged architecture / trap system will be excluded from synthesis. Hence, no interrupts, no exceptions and
|
disabled, the complete privileged architecture / trap system will be excluded from synthesis. Hence, no interrupts, no exceptions and
|
no machine information will be available.
|
no machine information will be available.
|
|
See section <<_zicsr_control_and_status_register_access_privileged_architecture>>.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _CPU_EXTENSION_RISCV_Zifencei_
|
===== _CPU_EXTENSION_RISCV_Zifencei_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **CPU_EXTENSION_RISCV_Zifencei** | _boolean_ | false
|
| **CPU_EXTENSION_RISCV_Zifencei** | _boolean_ | false
|
3+| Implement the instruction fetch synchronization instruction _fence.i_. For example, this option is required
|
3+| Implement the instruction fetch synchronization instruction `fence.i`. For example, this option is required
|
for self-modifying code (and/or for i-cache flushes).
|
for self-modifying code (and/or for i-cache flushes).
|
|
See section <<_zifencei_instruction_stream_synchronization>>.
|
|
|======
|
|
|
|
|
|
:sectnums!:
|
|
===== _CPU_EXTENSION_RISCV_Zmmul_
|
|
|
|
[cols="4,4,2"]
|
|
[frame="all",grid="none"]
|
|
|======
|
|
| **CPU_EXTENSION_RISCV_Zmmul** | _boolean_ | false
|
|
3+| Implement integer multiplication-only instructions when _true_. This is a sub-extensions of the `M` extension.
|
|
See section <<_zmmul_integer_multiplication>>.
|
|======
|
|======
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
| Line 333... |
Line 363... |
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **FAST_SHIFT_EN** | _boolean_ | false
|
| **FAST_SHIFT_EN** | _boolean_ | false
|
3+| When this generic is enabled the shifter unit of the CPU's ALU is implement as fast barrel shifter (requiring
|
3+| When this generic is set _true_ the shifter unit of the CPU's ALU is implemented as fast barrel shifter (requiring
|
more hardware resources).
|
more hardware resources). If it is set _false_ the CPU uses a serial shifter that only performs a single bit shift per cycle
|
|======
|
(small but slow).
|
|
|
|
|
:sectnums!:
|
|
===== _TINY_SHIFT_EN_
|
|
|
|
[cols="4,4,2"]
|
|
[frame="all",grid="none"]
|
|
|======
|
|
| **TINY_SHIFT_EN** | _boolean_ | false
|
|
3+| If this generic is enabled the shifter unit of the CPU's ALU is implemented as (slow but tiny) single-bit iterative shifter
|
|
(requires up to 32 clock cycles for a shift operations, but reducing hardware footprint). The configuration of
|
|
this generic is ignored if <<_fast_shift_en>> is _true_.
|
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _CPU_CNT_WIDTH_
|
===== _CPU_CNT_WIDTH_
|
| Line 458... |
Line 476... |
| **MEM_INT_IMEM_SIZE** | _natural_ | 16*1024
|
| **MEM_INT_IMEM_SIZE** | _natural_ | 16*1024
|
3+| Size in bytes of the processor internal instruction memory (IMEM). Has no effect when _MEM_INT_IMEM_EN_ is _false_.
|
3+| Size in bytes of the processor internal instruction memory (IMEM). Has no effect when _MEM_INT_IMEM_EN_ is _false_.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
|
===== _MEM_INT_IMEM_ROM_
|
|
|
|
[cols="4,4,2"]
|
|
[frame="all",grid="none"]
|
|
|======
|
|
| **MEM_INT_IMEM_ROM** | _boolean_ | false
|
|
3+| Implement processor-internal instruction memory as read-only memory, which will be initialized with the
|
|
application image at synthesis time. Has no effect when _MEM_INT_IMEM_EN_ is _false_.
|
|
|======
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
==== Internal Data Memory
|
==== Internal Data Memory
|
|
|
See sections <<_address_space>> and <<_data_memory_dmem>> for more information.
|
See sections <<_address_space>> and <<_data_memory_dmem>> for more information.
|
| Line 584... |
Line 590... |
|======
|
|======
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
|
==== Stream Link Interface
|
|
|
|
See section <<_stream_link_interface_slink>> for more information.
|
|
|
|
|
|
:sectnums!:
|
|
===== _SLINK_NUM_TX_
|
|
|
|
[cols="4,4,2"]
|
|
[frame="all",grid="none"]
|
|
|======
|
|
| **SLINK_NUM_TX** | _natural_ | 0
|
|
3+| Number of TX (send) links to implement. Valid values are 0..8.
|
|
|======
|
|
|
|
|
|
:sectnums!:
|
|
===== _SLINK_NUM_RX_
|
|
|
|
[cols="4,4,2"]
|
|
[frame="all",grid="none"]
|
|
|======
|
|
| **SLINK_NUM_RX** | _natural_ | 0
|
|
3+| Number of RX (receive) links to implement. Valid values are 0..8.
|
|
|======
|
|
|
|
|
|
:sectnums!:
|
|
===== _SLINK_TX_FIFO_
|
|
|
|
[cols="4,4,2"]
|
|
[frame="all",grid="none"]
|
|
|======
|
|
| **SLINK_TX_FIFO** | _natural_ | 1
|
|
3+| Internal FIFO depth for _all_ implemented TX links. Valid values are 1..32k and have to be a power of two.
|
|
|======
|
|
|
|
|
|
:sectnums!:
|
|
===== _SLINK_RX_FIFO_
|
|
|
|
[cols="4,4,2"]
|
|
[frame="all",grid="none"]
|
|
|======
|
|
| **SLINK_RX_FIFO** | _natural_ | 1
|
|
3+| Internal FIFO depth for _all_ implemented RX links. Valid values are 1..32k and have to be a power of two.
|
|
|======
|
|
|
|
|
|
// ####################################################################################################################
|
|
:sectnums:
|
|
==== External Interrupt Controller
|
|
|
|
See section <<_external_interrupt_controller_xirq>> for more information.
|
|
|
|
|
|
:sectnums!:
|
|
===== _XIRQ_NUM_CH_
|
|
|
|
[cols="4,4,2"]
|
|
[frame="all",grid="none"]
|
|
|======
|
|
| **XIRQ_NUM_CH** | _natural_ | 0
|
|
3+| Number of external interrupt channels o implement. Valid values are 0..32.
|
|
|======
|
|
|
|
|
|
:sectnums!:
|
|
===== _XIRQ_TRIGGER_TYPE_
|
|
|
|
[cols="4,4,2"]
|
|
[frame="all",grid="none"]
|
|
|======
|
|
| **XIRQ_TRIGGER_TYPE** | _std_ulogic_vector(31 downto 0)_ | 0xFFFFFFFF
|
|
3+| Interrupt trigger type configuration (one bit for each IRQ channel): `0` = level-triggered, '1' = edge triggered.
|
|
_XIRQ_TRIGGER_POLARITY_ generic is used to specify the actual level (high/low) or edge (falling/rising).
|
|
|======
|
|
|
|
|
|
:sectnums!:
|
|
===== _XIRQ_TRIGGER_POLARITY_
|
|
|
|
[cols="4,4,2"]
|
|
[frame="all",grid="none"]
|
|
|======
|
|
| **XIRQ_TRIGGER_POLARITY** | _std_ulogic_vector(31 downto 0)_ | 0xFFFFFFFF
|
|
3+| Interrupt trigger polarity configuration (one bit for each IRQ channel): `0` = low-level/falling-edge,
|
|
'1' = high-level/rising-edge. _XIRQ_TRIGGER_TYPE_ generic is used to specify the actual type (level or edge).
|
|
|======
|
|
|
|
|
|
// ####################################################################################################################
|
|
:sectnums:
|
==== Processor Peripheral/IO Modules
|
==== Processor Peripheral/IO Modules
|
|
|
See section <<_processor_internal_modules>> for more information.
|
See section <<_processor_internal_modules>> for more information.
|
|
|
|
|
| Line 744... |
Line 843... |
3+| Defines the size of the CFS output signal conduit (`cfs_out_o`). See section <<_custom_functions_subsystem_cfs>> for more information.
|
3+| Defines the size of the CFS output signal conduit (`cfs_out_o`). See section <<_custom_functions_subsystem_cfs>> for more information.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _IO_NCO_EN_
|
|
|
|
[cols="4,4,2"]
|
|
[frame="all",grid="none"]
|
|
|======
|
|
| **IO_NCO_EN** | _boolean_ | true
|
|
3+| Implement numerically-controlled oscillator (NCO) when _true_.
|
|
See section <<_numerically_controlled_oscillator_nco>> for more information.
|
|
|======
|
|
|
|
|
|
:sectnums!:
|
|
===== _IO_NEOLED_EN_
|
===== _IO_NEOLED_EN_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| Line 772... |
Line 859... |
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
=== Processor Interrupts
|
=== Processor Interrupts
|
|
|
[TIP]
|
The NEORV32 Processor provides several interrupt request signals (IRQs) for custom platform use.
|
The interrupt request signals have specific `mip` CSR bits (see <<_machine_trap_setup>>), specifc
|
|
`mie` CSR bits (see <<_machine_trap_handling>>) and specifc `mcause` CSR trap codes and trap
|
|
priorities. For more information (also regarding the signaling protocol) see section <<_traps_exceptions_and_interrupts>>.
|
|
|
|
**RISC-V Standard Interrupts**
|
|
|
:sectnums:
|
|
==== RISC-V Standard Interrupts
|
|
|
The processor setup features the standard RISC-V interrupt lines for "machine timer interrupt", "machine
|
The processor setup features the standard RISC-V interrupt lines for "machine timer interrupt", "machine
|
software interrupt" and "machine external interrupt". The software and external interrupt lines are available
|
software interrupt" and "machine external interrupt". Their usage is defined by the RISC-V privileged architecture
|
via the processor's top entity. By default, the timer interrupt is connected to the internal machine timer
|
specifications. However, bare-metal system can also repurpose these interrupts. See CPU section
|
MTIME timer unit (<<_machine_system_timer_mtime>>). If this module has not been enabled for
|
<<_traps_exceptions_and_interrupts>> for more information.
|
synthesis, the machine timer interrupt is also available via the processor's top entity.
|
|
|
|
**NEORV32-Specific Fast Interrupt Requests**
|
[cols="<3,^2,<11"]
|
|
[options="header",grid="rows"]
|
|
|=======================
|
|
| Top signal | Width | Description
|
|
| `mtime_irq_i` | 1 | Machine timer interrupt from _processor-external_ MTIME unit. This IRQ is only available if the processor-internal MTIME unit is not used (<<_io_mtime_en>> = false).
|
|
| `msw_irq_i` | 1 | Machine software interrupt. This interrupt is used for inter-processor interrupts in multi-core systems. However, it can also be used for any custom purpose.
|
|
| `mext_irq_i` | 1 | Machine external interrupt. This interrupt is used for any processor-external interrupt source (like a platform interrupt controller).
|
|
|=======================
|
|
|
As part of the custom/NEORV32-specific CPU extensions, the CPU features 16 fast interrupt request signals
|
[NOTE]
|
(`FIRQ0` – `FIRQ15`).
|
These IRQs trigger on high-level.
|
|
|
|
|
|
:sectnums:
|
|
==== Non-Maskable Interrupt
|
|
|
|
[cols="<3,^2,<11"]
|
|
[options="header",grid="rows"]
|
|
|=======================
|
|
| Top signal | Width | Description
|
|
| `nm_irq_i` | 1 | Non-maskable interrupt.
|
|
|=======================
|
|
|
The fast interrupt request signals are divided into two groups. The FIRQs with higher priority (FIRQ0 –
|
The processor features a single non-maskable interrupt source via the `nm_irq_i` top
|
FIRQ9) are dedicated for processor-internal usage. The FIRQs with lower priority (FIRQ10 – FIRQ15) are
|
entity signal that can be used to signal _critical system conditions_. This interrupt source _cannot_ be masked/disabled.
|
available for custom usage via the processor's top entity signal `soc_firq_i`.
|
See CPU section <<_traps_exceptions_and_interrupts>> for more information.
|
|
|
The mapping of the 16 FIRQ channels is shown in the following table (the channel number corresponds to the FIRQ priority):
|
[NOTE]
|
|
This IRQ triggers on high-level.
|
|
|
|
|
|
:sectnums:
|
|
==== Platform External Interrupts
|
|
|
|
[cols="<3,^2,<11"]
|
|
[options="header",grid="rows"]
|
|
|=======================
|
|
| Top signal | Width | Description
|
|
| `xirq_i` | up to 32 | External platform interrupts (user-defined).
|
|
|=======================
|
|
|
|
The processor provides an optional interrupt controller for up to 32 user-defined external interrupts
|
|
(see section <<_external_interrupt_controller_xirq>>). These external IRQs are mapped to a _single_ CPU
|
|
fast interrupt request so a software handler is required to differentiate / prioritize these interrupts.
|
|
|
|
[NOTE]
|
|
The trigger for these interrupt can be defines via generics. See section
|
|
<<_external_interrupt_controller_xirq>> for more information.
|
|
|
|
|
|
:sectnums:
|
|
==== NEORV32-Specific Fast Interrupt Requests
|
|
|
|
As part of the custom/NEORV32-specific CPU extensions, the CPU features 16 fast interrupt request signals
|
|
(`FIRQ0` – `FIRQ15`). These are used for _processor-internal_ modules only (for example for the communication
|
|
interfaces to signal "available incoming data" or "ready to send new data").
|
|
|
|
The mapping of the 16 FIRQ channels is shown in the following table (the channel number also corresponds to
|
|
the according FIRQ priority; 0 = highest, 15 = lowest):
|
|
|
.NEORV32 fast interrupt channel mapping
|
.NEORV32 fast interrupt channel mapping
|
[cols="^1,<2,<7"]
|
[cols="^1,<2,<7"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Channel | Source | Description
|
| Channel | Source | Description
|
| 0 | _WDT_ | watchdog timeout interrupt
|
| 0 | <<_watchdog_timer_wdt,WDT>> | watchdog timeout interrupt
|
| 1 | _CFS_ | custom functions subsystem (CFS) interrupt (user-defined)
|
| 1 | <<_custom_functions_subsystem_cfs,CFS>> | custom functions subsystem (CFS) interrupt (user-defined)
|
| 2 | _UART0_ (RXD) | UART0 data received interrupt (RX complete)
|
| 2 | <<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>> | UART0 data received interrupt (RX complete)
|
| 3 | _UART0_ (TXD) | UART0 sending done interrupt (TX complete)
|
| 3 | <<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>> | UART0 sending done interrupt (TX complete)
|
| 4 | _UART1_ (RXD) | UART1 data received interrupt (RX complete)
|
| 4 | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 data received interrupt (RX complete)
|
| 5 | _UART1_ (TXD) | UART1 sending done interrupt (TX complete)
|
| 5 | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 sending done interrupt (TX complete)
|
| 6 | _SPI_ | SPI transmission done interrupt
|
| 6 | <<_serial_peripheral_interface_controller_spi,SPI>> | SPI transmission done interrupt
|
| 7 | _TWI_ | TWI transmission done interrupt
|
| 7 | <<_two_wire_serial_interface_controller_twi,TWI>> | TWI transmission done interrupt
|
| 8 | _GPIO_ | GPIO input pin-change interrupt
|
| 8 | <<_external_interrupt_controller_xirq,XIRQ>> | External interrupt controller interrupt
|
| 9 | _NEOLED_ | NEOLED buffer TX empty / not full interrupt
|
| 9 | <<_smart_led_interface_neoled,NEOLED>> | NEOLED buffer TX empty / not full interrupt
|
| 10:15 | `soc_firq_i(5:0)` | Custom platform use; available via processor's top signal
|
| 10 | <<_stream_link_interface_slink,SLINK>> | RX data received
|
|
| 11 | <<_stream_link_interface_slink,SLINK>> | TX data send
|
|
| 12:15 | - | _reserved_, cannot fire
|
|=======================
|
|=======================
|
|
|
**Non-Maskable Interrupt**
|
|
|
|
The NEORV32 features a single non-maskable interrupt source via the `nm_irq_i` top
|
|
entity signal that can be used to signal critical system conditions. This interrupt source _cannot_ be disabled. Hence, it does _not_ provide
|
|
configuration/status flags in the `mie` and `mip` CSRs. The RISC-V-compatible `mcause` value `0x80000000` is used to indicate the non-maskable interrupt.
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
=== Address Space
|
=== Address Space
|
|
|
By default, the total 32-bit (4GB) address space of the NEORV32 Processor is divided into four main regions:
|
The NEORV32 Processor provides 32-bit physical addresses accessing up to 4GB of address space.
|
|
By default, this address space is divided into four main regions:
|
|
|
1. Instruction memory (IMEM) space – for instructions and constants.
|
1. **Instruction address space** – for instructions (=code) and constants. A configurable section of this address space is used by
|
2. Data memory (DMEM) space – for application runtime data (heap, stack, etc.).
|
internal and/or external _instruction memory_ (IMEM).
|
3. Bootloader ROM address space – for the processor-internal bootloader.
|
2. **Data address space** – for application runtime data (heap, stack, etc.). A configurable section of this address space is used by
|
4. IO/peripheral address space – for the processor-internal IO/peripheral devices (e.g., UART).
|
internal and/or external _data memory_ (DMEM).
|
|
3. **Bootloader address space**. A _fixed_ section of this address space is used by
|
.NEORV32 processor - address space (default configuration)
|
internal _bootloader memory_ (BOOTLDROM).
|
image::address_space.png[900]
|
4. **IO/peripheral address space** – for the processor-internal IO/peripheral devices (e.g., UART).
|
|
|
[TIP]
|
[TIP]
|
These four memory regions are handled by the linker when compiling a NEORV32 executable.
|
These four memory regions are handled by the linker when compiling a NEORV32 executable.
|
See section <<_executable_image_format>> for more information.
|
See section <<_executable_image_format>> for more information.
|
|
|
**Address Space Layout**
|
.NEORV32 processor - address space (default configuration)
|
|
image::address_space.png[900]
|
The general address space layout consists of two main configuration constants: `ispace_base_c` defining
|
|
the base address of the instruction memory address space and `dspace_base_c` defining the base address of
|
|
the data memory address space. Both constants are defined in the NEORV32 VHDL package file
|
|
`rtl/core/neorv32_package.vhd`:
|
|
|
|
[source,vhdl]
|
|
----
|
|
-- Architecture Configuration ----------------------------------------------------
|
|
-- ----------------------------------------------------------------------------------
|
|
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000";
|
|
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000";
|
|
----
|
|
|
|
The default configuration assumes the instruction memory address space starting at address _0x00000000_
|
|
and the data memory address space starting at _0x80000000_. Both values can be modified for a specific
|
|
setup and the address space may overlap or can be completely identical.
|
|
|
|
The base address of the bootloader (at _0xFFFF0000_) and the IO region (at _0xFFFFFF00_) for the peripheral
|
|
devices are also defined in the package and are fixed. These address regions cannot be used for other
|
|
applications – even if the bootloader or all IO devices are not implemented.
|
|
|
|
[WARNING]
|
|
When using the processor-internal data and/or instruction memories (DMEM/IMEM) and using a non-default
|
|
configuration for the `dspace_base_c` and/or `ispace_base_c` base addresses, the
|
|
following requirements have to be fulfilled:
|
|
**1.** Both base addresses have to be aligned to a 4-byte boundary.
|
|
**2.** Both base addresses have to be aligned to the according internal memory sizes.
|
|
|
|
:sectnums:
|
:sectnums:
|
==== CPU Data and Instruction Access
|
==== CPU Data and Instruction Access
|
|
|
The CPU can access all of the 4GB address space from the instruction fetch interface (**I**) and also from the
|
The CPU can access all of the 4GB address space from the instruction fetch interface (**I**) and also from the
|
| Line 896... |
Line 1003... |
accessed from programs running in less-privileged user mode. For example, if the system relies on
|
accessed from programs running in less-privileged user mode. For example, if the system relies on
|
a periodic interrupt from the _MTIME_ timer unit, user-level programs could alter the _MTIME_
|
a periodic interrupt from the _MTIME_ timer unit, user-level programs could alter the _MTIME_
|
configuration corrupting this interrupt. This kind of security issues can be compensated using the
|
configuration corrupting this interrupt. This kind of security issues can be compensated using the
|
PMP system (see <<_machine_physical_memory_protection>>).
|
PMP system (see <<_machine_physical_memory_protection>>).
|
|
|
|
|
|
:sectnums:
|
|
==== Address Space Layout
|
|
|
|
The general address space layout consists of two main configuration constants: `ispace_base_c` defining
|
|
the base address of the _instruction memory address space_ and `dspace_base_c` defining the base address of
|
|
the _data memory address space_. Both constants are defined in the NEORV32 VHDL package file
|
|
`rtl/core/neorv32_package.vhd`:
|
|
|
|
[source,vhdl]
|
|
----
|
|
-- Architecture Configuration ----------------------------------------------------
|
|
-- ----------------------------------------------------------------------------------
|
|
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000";
|
|
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000";
|
|
----
|
|
|
|
The default configuration assumes the _instruction memory address space_ starting at address _0x00000000_
|
|
and the _data memory address space_ starting at _0x80000000_. Both values can be modified for a specific
|
|
setup and the address space may overlap or can be completely identical. Make sure that both base addresses
|
|
are _aligned_ to a 4-byte boundary.
|
|
|
|
[NOTE]
|
|
The base address of the internal bootloader (at _0xFFFF0000_) and the internal IO region (at _0xFFFFFE00_) for
|
|
peripheral devices are also defined in the package and are fixed. These address regions cannot not be used for other
|
|
applications – even if the bootloader or all IO devices are not implemented - without modifying the core's
|
|
hardware sources.
|
|
|
|
|
:sectnums:
|
:sectnums:
|
==== Physical Memory Attributes
|
==== Physical Memory Attributes
|
|
|
The processor setup defines four simple attributes for the four processor-internal address space regions:
|
The processor setup defines fixed attributes for the four processor-internal address space regions.
|
|
Accessing a memory region in a way that violates any of these attributes will raise an according
|
|
access exception..
|
|
|
* `r` – read access (from CPU data access interface, e.g. via "load")
|
* `r` – read access (from CPU data access interface, e.g. via "load")
|
* `w` – write access (from CPU data access interface, e.g. via "store")
|
* `w` – write access (from CPU data access interface, e.g. via "store")
|
* `x` – execute access (from CPU instruction fetch interface)
|
* `x` – execute access (from CPU instruction fetch interface)
|
* `a` – atomic access (from CPU data access interface)
|
* `a` – atomic access (from CPU data access interface)
|
* `8` – byte (8-bit)-accessible (when writing)
|
* `8` – byte (8-bit)-accessible (when writing)
|
* `16` – half-word (16-bit)-accessible (when writing)
|
* `16` – half-word (16-bit)-accessible (when writing)
|
* `32` – word (32-bit)-accessible (when writing)
|
* `32` – word (32-bit)-accessible (when writing)
|
|
|
The following table shows the provided physical memory attributes of each region. Additional attributes (like
|
[NOTE]
|
denying execute right for certain region of the IMEM) can be provided using the RISC-V <<_machine_physical_memory_protection>> extension.
|
Read accesses (i.e. loads) can always access data in word, half-word and byte quantities (requiring an accordingly aligned address).
|
|
|
[cols="^1,^2,^2,^3,^2"]
|
[cols="^1,^2,^2,^3,^2"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| # | Region | Base address | Size | Attributes
|
| # | Region | Base address | Size | Attributes
|
| Line 922... |
Line 1060... |
| 3 | bootloader ROM | 0xffff0000 | up to 32kB| `r/x/a`
|
| 3 | bootloader ROM | 0xffff0000 | up to 32kB| `r/x/a`
|
| 2 | DMEM | 0x80000000 | up to 2GB (-64kB) | `r/w/x/a/8/16/32`
|
| 2 | DMEM | 0x80000000 | up to 2GB (-64kB) | `r/w/x/a/8/16/32`
|
| 1 | IMEM | 0x00000000 | up to 2GB | `r/w/x/a/8/16/32`
|
| 1 | IMEM | 0x00000000 | up to 2GB | `r/w/x/a/8/16/32`
|
|=======================
|
|=======================
|
|
|
Only the CPU of the processor has access to the internal memories and IO devices, hence all accesses are
|
[TIP]
|
always exclusive. Accessing a memory region in a way that violates the provided attributes will trigger a
|
The following table shows the provided physical memory attributes of each region. Additional attributes (for example
|
load/store/instruction fetch access exception or will return a failed atomic access result, respectively.
|
controlling certain right for specific address space regions) can be provided using the RISC-V <<_machine_physical_memory_protection>> extension.
|
|
|
The physical memory attributes of memories and/or devices connected via the external bus interface have to
|
|
defined by those components or the interconnection fabric.
|
|
|
|
:sectnums:
|
:sectnums:
|
==== Internal Memories
|
==== Memory Configuration
|
|
|
|
The NEORV32 Processor was designed to provide maximum flexibility for the memory configuration.
|
|
The processor can populate the _instruction address space_ and/or the _data address space_ with **internal memories**
|
|
for instructions (IMEM) and data (DMEM). Processor **external memories** can be used as an _alternative_ or even _in combination_ with
|
|
the internal ones. The figure below show some exemplary memory configurations.
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The processor can implement internal memories for instructions (IMEM) and data (DMEM), which will be
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.Exemplary memory configurations
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mapped to FPGA block RAMs. The implementation of these memories is controlled via the boolean
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image::neorv32_memory_configurations.png[800]
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<<_mem_int_imem_en>> and <<_mem_int_dmem_en>> generics.
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The size of these memories are configured via the _MEM_INT_IMEM_SIZE_ and _MEM_INT_DMEM_SIZE_
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:sectnums!:
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generics (in bytes), respectively. The processor-internal instruction memory (IMEM) can optionally be
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===== Internal Memories
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implemented as true ROM (<<_mem_int_imem_rom>>), which is initialized with the application code during
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synthesis.
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The processor-internal memories (<<_instruction_memory_imem>> and <<_data_memory_dmem>>) are enabled (=implemented)
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via the <<_mem_int_imem_en>> and <<_mem_int_dmem_en>> generics. Their sizes are configures via the according
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<<_mem_int_imem_size>> and <<_mem_int_dmem_size>> generics.
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If the processor-internal IMEM is implemented, it is located right at the base address of the instruction
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If the processor-internal IMEM is implemented, it is located right at the base address of the instruction
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address space (default `ispace_base_c` = _0x00000000_). Vice versa, the processor-internal data memory is
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address space (default `ispace_base_c` = _0x00000000_). Vice versa, the processor-internal data memory is
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located right at the beginning of the data address space (default `dspace_base_c` = _0x80000000_) when
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located right at the beginning of the data address space (default `dspace_base_c` = _0x80000000_) when
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implemented.
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implemented.
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:sectnums:
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[TIP]
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==== External Memory/Bus Interface
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The default processor setup uses only _internal_ memories.
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[NOTE]
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If the IMEM (internal or external) is less than the (default) maximum size (2GB), there is
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a "dead address space" between it and the DMEM. This provides an additional safety feature
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since data corrupting scenarios like stack overflow cannot directly corrupt the content of the IMEM:
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any access to the "dead address space" in between will raise an exception that can be caught
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by the runtime environment.
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:sectnums!:
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===== External Memories
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If external memories (or further IP modules) shall be connected via the _processor's external bus interface_,
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the interface has to be enabled via <<_mem_ext_en>> generic (=_true_). More information regarding this interface can be
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|
found in section <<_processor_external_memory_interface_wishbone_axi4_lite>>.
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Any CPU access (data or instructions), which does not fulfill one of the following conditions, is forwarded
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Any CPU access (data or instructions), which does not fulfill _at least one_ of the following conditions, is forwarded
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to the <<_processor_external_memory_interface_wishbone_axi4_lite>>:
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via the processor's bus interface to external components:
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* access to the processor-internal IMEM and processor-internal IMEM is implemented
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* access to the processor-internal IMEM and processor-internal IMEM is implemented
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* access to the processor-internal DMEM and processor-internal DMEM is implemented
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* access to the processor-internal DMEM and processor-internal DMEM is implemented
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* access to the bootloader ROM and beyond → addresses >= _BOOTROM_BASE_ (default 0xFFFF0000) will never be forwarded to the external memory interface
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* access to the bootloader ROM and beyond → addresses >= _BOOTROM_BASE_ (default 0xFFFF0000) will never be forwarded to the external memory interface
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The external bus interface is available when the <<_mem_ext_en>> generic is _true_. If this interface is
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If no (or not all) processor-internal memories are implemented, the according base addresses are mapped to external memories.
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deactivated, any access exceeding the internal memories or peripheral devices will trigger a bus access fault
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For example, if the processor-internal IMEM is not implemented (<<_mem_int_imem_en>> = _false_), the processor will forward
|
exception. If <<_mem_ext_timeout>> is greater than zero any external bus access that is not acknowledged or terminated
|
any access to the instruction address space (starting at `ispace_base_c`) via the external bus interface to the external
|
within <<_mem_ext_timeout>> clock cycles will auto-timeout and raise the according bus fault exception.
|
memory system.
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|
|
|
[NOTE]
|
|
If the external interface is deactivated, any access exceeding the internal memory address space (instruction, data, bootloader) or
|
|
the internal peripheral address space will trigger a bus access fault exception.
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|
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:sectnums:
|
|
==== Boot Configuration
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|
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|
Due to the flexible memory configuration concept, the NEORV32 Processor provides several different boot concepts.
|
|
The figure below shows the exemplary concepts for the two most common boot scenarios.
|
|
|
|
.NEORV32 boot configurations
|
|
image::neorv32_boot_configurations.png[800]
|
|
|
|
[NOTE]
|
|
The configuration of internal or external data memory (DMEM; <<_mem_int_dmem_en>> = _true_ / _false_) is not further
|
|
relevant for the boot configuration itself. Hence, it is not further illustrated here.
|
|
|
|
There are two general boot scenarios: _Indirect Boot_ (1a and 1b) and _Direct Boot_ (2a and 2b) configured via the
|
|
<<_int_bootloader_en>> generic If this generic is set **true** the _indirect_ boot scenario is used. This is also the
|
|
default boot configuration of the processor. If <<_int_bootloader_en>> is set **false** the _direct_ boot scenario is used.
|
|
|
|
[NOTE]
|
|
Please note that the provided boot scenarios are just exemplary setups that (should) fit most common requirements.
|
|
Much more sophisticated boot scenarios are possible by combining internal and external memories. For example, the default
|
|
internal bootloader could be used as first-level bootloader that loads (from extern SPI flash) a second-level bootloader
|
|
that is placed and execute in internal IMEM. This second-level bootloader could then fetch the actual application and
|
|
store it to external _data_ memory and transfers CPU control to that.
|
|
|
|
:sectnums!:
|
|
===== Indirect Boot
|
|
|
|
The _indirect_ boot scenarios **1a** and **1b** use the processor-internal <<_bootloader>>. This general setup is enabled
|
|
by setting the <<_int_bootloader_en>> generic to true, which will implement the processor-internal <<_bootloader_rom_bootrom>>.
|
|
This read-only memory is pre-initialized during synthesis with the default bootloader firmware.
|
|
|
|
The bootloader provides several options to upload an executable (via UART or from external SPI flash) and store it to
|
|
the _instruction address space_ so the CPU can execute it. Boot scenario **1a** uses the processor-internal IMEM
|
|
(<<_mem_int_imem_en>> = _true_). This scenario implements the internal <<_instruction_memory_imem>> as non-initialized
|
|
RAM so the bootloader can write the actual executable to it.
|
|
|
|
Boot scenario **1b** uses a processor-external IMEM (<<_mem_int_imem_en>> = _false_) that is connected via the processor's
|
|
bus interface. In this scenario the internal <<_instruction_memory_imem>> is not implemented at all and the bootloader will
|
|
write the executable to the processor-external memory.
|
|
|
|
:sectnums!:
|
|
===== Direct Boot
|
|
|
|
The _direct_ boot scenarios **2a** and **2b** do not use the processor-internal bootloader. Hence, the <<_int_bootloader_en>>
|
|
generic is set _false_. In this configuration the <<_bootloader_rom_bootrom>> is not implemented at all and the CPU will
|
|
directly begin executing code from the instruction address space after reset. A "pre-initialization mechanism is required
|
|
in order to provide an executable _in_ memory.
|
|
|
|
Boot scenario **2a** uses the processor-internal IMEM (<<_mem_int_imem_en>> = _true_) that is implemented as _read-only memory_
|
|
in this scenario. It is pre-initialized (by the bitstream) with the actual application executable.
|
|
|
|
In contrast, boot scenario **2b** uses a processor-external IMEM (<<_mem_int_imem_en>> = _false_). In this scenario the
|
|
system designer is responsible for providing a initialized external memory that contains the actual application to be executed.
|
|
|
|
|
|
|
|
|
// ####################################################################################################################
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// ####################################################################################################################
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| Line 1068... |
Line 1283... |
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include::soc_icache.adoc[]
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include::soc_icache.adoc[]
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include::soc_wishbone.adoc[]
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include::soc_wishbone.adoc[]
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include::soc_slink.adoc[]
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include::soc_gpio.adoc[]
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include::soc_gpio.adoc[]
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include::soc_wdt.adoc[]
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include::soc_wdt.adoc[]
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include::soc_mtime.adoc[]
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include::soc_mtime.adoc[]
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| Line 1086... |
Line 1303... |
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include::soc_trng.adoc[]
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include::soc_trng.adoc[]
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include::soc_cfs.adoc[]
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include::soc_cfs.adoc[]
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include::soc_nco.adoc[]
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include::soc_neoled.adoc[]
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include::soc_neoled.adoc[]
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include::soc_xirq.adoc[]
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include::soc_sysinfo.adoc[]
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include::soc_sysinfo.adoc[]
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