| Line 11... |
Line 11... |
**Key Features**
|
**Key Features**
|
|
|
* _optional_ processor-internal data and instruction memories (<<_data_memory_dmem,**DMEM**>>/<<_instruction_memory_imem,**IMEM**>>) + cache (<<_processor_internal_instruction_cache_icache,**iCACHE**>>)
|
* _optional_ processor-internal data and instruction memories (<<_data_memory_dmem,**DMEM**>>/<<_instruction_memory_imem,**IMEM**>>) + cache (<<_processor_internal_instruction_cache_icache,**iCACHE**>>)
|
* _optional_ internal bootloader (<<_bootloader_rom_bootrom,**BOOTROM**>>) with UART console & SPI flash boot option
|
* _optional_ internal bootloader (<<_bootloader_rom_bootrom,**BOOTROM**>>) with UART console & SPI flash boot option
|
* _optional_ machine system timer (<<_machine_system_timer_mtime,**MTIME**>>), RISC-V-compatible
|
* _optional_ machine system timer (<<_machine_system_timer_mtime,**MTIME**>>), RISC-V-compatible
|
* _optional_ two independent universal asynchronous receivers and transmitters (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,**UART0**>>, <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,**UART1**>>) with optional hardware flow control (RTS/CTS)
|
* _optional_ two independent universal asynchronous receivers and transmitters (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,**UART0**>>, <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,**UART1**>>) with optional hardware flow control (RTS/CTS) and optional RX/TX FIFOs
|
* _optional_ 8/16/24/32-bit serial peripheral interface controller (<<_serial_peripheral_interface_controller_spi,**SPI**>>) with 8 dedicated CS lines
|
* _optional_ 8/16/24/32-bit serial peripheral interface controller (<<_serial_peripheral_interface_controller_spi,**SPI**>>) with 8 dedicated CS lines
|
* _optional_ two wire serial interface controller (<<_two_wire_serial_interface_controller_twi,**TWI**>>), compatible to the I²C standard
|
* _optional_ two wire serial interface controller (<<_two_wire_serial_interface_controller_twi,**TWI**>>), compatible to the I²C standard
|
* _optional_ general purpose parallel IO port (<<_general_purpose_input_and_output_port_gpio,**GPIO**>>), 64xOut, 64xIn
|
* _optional_ general purpose parallel IO port (<<_general_purpose_input_and_output_port_gpio,**GPIO**>>), 64xOut, 64xIn
|
* _optional_ 32-bit external bus interface, Wishbone b4 / AXI4-Lite compatible (<<_processor_external_memory_interface_wishbone_axi4_lite,**WISHBONE**>>)
|
* _optional_ 32-bit external bus interface, Wishbone b4 / AXI4-Lite compatible (<<_processor_external_memory_interface_wishbone_axi4_lite,**WISHBONE**>>)
|
* _optional_ 32-bit stream link interface with up to 8 independent links, AXI4-Stream compatible (<<_stream_link_interface_slink,**SLINK**>>)
|
* _optional_ 32-bit stream link interface with up to 8 independent links, AXI4-Stream compatible (<<_stream_link_interface_slink,**SLINK**>>)
|
| Line 794... |
Line 794... |
more information.
|
more information.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
|
===== _IO_UART0_RX_FIFO_
|
|
|
|
[cols="4,4,2"]
|
|
[frame="all",grid="none"]
|
|
|======
|
|
| **IO_UART0_RX_FIFO** | _natural_ | 1
|
|
3+| UART0 receiver FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
|
|
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
|
|
more information.
|
|
|======
|
|
|
|
|
|
:sectnums!:
|
|
===== _IO_UART0_TX_FIFO_
|
|
|
|
[cols="4,4,2"]
|
|
[frame="all",grid="none"]
|
|
|======
|
|
| **IO_UART0_TX_FIFO** | _natural_ | 1
|
|
3+| UART0 transmitter FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
|
|
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
|
|
more information.
|
|
|======
|
|
|
|
|
|
:sectnums!:
|
===== _IO_UART1_EN_
|
===== _IO_UART1_EN_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| Line 806... |
Line 832... |
See section <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1>> for more information.
|
See section <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1>> for more information.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
|
===== _IO_UART1_RX_FIFO_
|
|
|
|
[cols="4,4,2"]
|
|
[frame="all",grid="none"]
|
|
|======
|
|
| **IO_UART1_RX_FIFO** | _natural_ | 1
|
|
3+| UART1 receiver FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
|
|
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
|
|
more information.
|
|
|======
|
|
|
|
|
|
:sectnums!:
|
|
===== _IO_UART1_TX_FIFO_
|
|
|
|
[cols="4,4,2"]
|
|
[frame="all",grid="none"]
|
|
|======
|
|
| **IO_UART1_TX_FIFO** | _natural_ | 1
|
|
3+| UART1 transmitter FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
|
|
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
|
|
more information.
|
|
|======
|
|
|
|
|
|
:sectnums!:
|
===== _IO_SPI_EN_
|
===== _IO_SPI_EN_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| Line 962... |
Line 1014... |
| `mext_irq_i` | 1 | Machine external interrupt. This interrupt is used for any processor-external interrupt source (like a platform interrupt controller).
|
| `mext_irq_i` | 1 | Machine external interrupt. This interrupt is used for any processor-external interrupt source (like a platform interrupt controller).
|
|=======================
|
|=======================
|
|
|
.Trigger type
|
.Trigger type
|
[IMPORTANT]
|
[IMPORTANT]
|
These IRQs trigger on **high-level** and must _stay asserted_ until explicitly acknowledged by the CPU (for example
|
The fast interrupt request channel trigger on **high-level** and have to stay asserted until explicitly acknowledged
|
by writing to a specific memory-mapped register).
|
by the software (for example by writing to a specifc memory-mapped register). Hence, pending interrupts remain pending
|
|
as long as the interrupt-causing device's state fulfills it's interrupt condition(s).
|
|
|
|
|
:sectnums:
|
:sectnums:
|
==== Platform External Interrupts
|
==== Platform External Interrupts
|
|
|
| Line 984... |
Line 1037... |
|
|
.Trigger type
|
.Trigger type
|
[IMPORTANT]
|
[IMPORTANT]
|
The trigger for these interrupt can be defined via generics. See section
|
The trigger for these interrupt can be defined via generics. See section
|
<<_external_interrupt_controller_xirq>> for more information. Depending on the trigger type, users can
|
<<_external_interrupt_controller_xirq>> for more information. Depending on the trigger type, users can
|
implement custom acknowledge mechanisms.
|
implement custom acknowledge mechanisms. All _external interrupts_ are mapped to a single processor-internal
|
|
_fast interrupt request_ (see below).
|
|
|
|
|
:sectnums:
|
:sectnums:
|
==== NEORV32-Specific Fast Interrupt Requests
|
==== NEORV32-Specific Fast Interrupt Requests
|
|
|
As part of the custom/NEORV32-specific CPU extensions, the CPU features 16 fast interrupt request signals
|
As part of the custom/NEORV32-specific CPU extensions, the CPU features 16 fast interrupt request signals
|
(`FIRQ0` – `FIRQ15`). These are used for _processor-internal_ modules only (for example for the communication
|
(`FIRQ0` - `FIRQ15`). These are reserved for _processor-internal_ modules only (for example for the communication
|
interfaces to signal "available incoming data" or "ready to send new data").
|
interfaces to signal "available incoming data" or "ready to send new data").
|
|
|
The mapping of the 16 FIRQ channels is shown in the following table (the channel number also corresponds to
|
The mapping of the 16 FIRQ channels is shown in the following table (the channel number also corresponds to
|
the according FIRQ priority; 0 = highest, 15 = lowest):
|
the according FIRQ priority; 0 = highest, 15 = lowest):
|
|
|
| Line 1011... |
Line 1065... |
| 4 | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 data received interrupt (RX complete)
|
| 4 | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 data received interrupt (RX complete)
|
| 5 | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 sending done interrupt (TX complete)
|
| 5 | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 sending done interrupt (TX complete)
|
| 6 | <<_serial_peripheral_interface_controller_spi,SPI>> | SPI transmission done interrupt
|
| 6 | <<_serial_peripheral_interface_controller_spi,SPI>> | SPI transmission done interrupt
|
| 7 | <<_two_wire_serial_interface_controller_twi,TWI>> | TWI transmission done interrupt
|
| 7 | <<_two_wire_serial_interface_controller_twi,TWI>> | TWI transmission done interrupt
|
| 8 | <<_external_interrupt_controller_xirq,XIRQ>> | External interrupt controller interrupt
|
| 8 | <<_external_interrupt_controller_xirq,XIRQ>> | External interrupt controller interrupt
|
| 9 | <<_smart_led_interface_neoled,NEOLED>> | NEOLED buffer TX empty / not full interrupt
|
| 9 | <<_smart_led_interface_neoled,NEOLED>> | NEOLED TX buffer interrupt
|
| 10 | <<_stream_link_interface_slink,SLINK>> | RX data received
|
| 10 | <<_stream_link_interface_slink,SLINK>> | RX data buffer interrupt
|
| 11 | <<_stream_link_interface_slink,SLINK>> | TX data send
|
| 11 | <<_stream_link_interface_slink,SLINK>> | TX data buffer interrupt
|
| 12:15 | - | _reserved_, will never fire
|
| 12:15 | - | _reserved_, will never fire
|
|=======================
|
|=======================
|
|
|
.Trigger type
|
.Trigger type
|
[IMPORTANT]
|
[IMPORTANT]
|
The fast interrupt request channel trigger on a single **rising-edge** and do not require any kind of explicit
|
The fast interrupt request channel trigger on **high-level** and have to stay asserted until explicitly acknowledged
|
acknowledgment at all.
|
by the software (for example by writing to a specifc memory-mapped register). Hence, pending interrupts remain pending
|
|
as long as the interrupt-causing device's state fulfills it's interrupt condition(s).
|
|
|
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
=== Address Space
|
=== Address Space
|
|
|
The NEORV32 Processor provides 32-bit physical addresses accessing up to 4GB of address space.
|
The NEORV32 Processor provides a 32-bit / 4GB (physical) address space
|
By default, this address space is divided into four main regions:
|
By default, this address space is divided into five main regions:
|
|
|
1. **Instruction address space** – for instructions (=code) and constants. A configurable section of this address space is used by
|
1. **Instruction address space** - memory address space for instructions (=code) and constants.
|
internal and/or external _instruction memory_ (IMEM).
|
A configurable section of this address space is used by the internal/external _instruction memory_ (<<_mem_int_imem_size>> for the internal IMEM).
|
2. **Data address space** – for application runtime data (heap, stack, etc.). A configurable section of this address space is used by
|
2. **Data address space** - memory address space for application runtime data (heap, stack, etc.).
|
internal and/or external _data memory_ (DMEM).
|
A configurable section of this address space is used by the internal/external _data memory_ (<<_mem_int_dmem_size>> for the internal DMEM).
|
3. **Bootloader address space**. A _fixed_ section of this address space is used by
|
3. **Bootloader address space**. A _fixed_ section of this address space is used by the
|
internal _bootloader memory_ (BOOTLDROM).
|
internal _bootloader memory_ (BOOTLDROM).
|
4. **IO/peripheral address space** – for the processor-internal IO/peripheral devices (e.g., UART).
|
4. **On-Chip Debugger address space**. This _fixed_ section is entirely used by the processor's <<_on_chip_debugger_ocd>>.
|
|
5. **IO/peripheral address space**. Also a _fixed_ section used for the processor-internal memory-mapped IO/peripheral devices (e.g., UART).
|
[TIP]
|
|
These four memory regions are handled by the linker when compiling a NEORV32 executable.
|
|
See section <<_executable_image_format>> for more information.
|
|
|
|
.NEORV32 processor - address space (default configuration)
|
.NEORV32 processor - address space (default configuration)
|
image::address_space.png[900]
|
image::address_space.png[900]
|
|
|
|
|
| Line 1100... |
Line 1152... |
are _aligned_ to a 4-byte boundary.
|
are _aligned_ to a 4-byte boundary.
|
|
|
[NOTE]
|
[NOTE]
|
The base address of the internal bootloader (at _0xFFFF0000_) and the internal IO region (at _0xFFFFFE00_) for
|
The base address of the internal bootloader (at _0xFFFF0000_) and the internal IO region (at _0xFFFFFE00_) for
|
peripheral devices are also defined in the package and are fixed. These address regions cannot not be used for other
|
peripheral devices are also defined in the package and are fixed. These address regions cannot not be used for other
|
applications – even if the bootloader or all IO devices are not implemented - without modifying the core's
|
applications - even if the bootloader or all IO devices are not implemented - without modifying the core's
|
hardware sources.
|
hardware sources.
|
|
|
|
|
:sectnums:
|
:sectnums:
|
==== Physical Memory Attributes
|
==== Physical Memory Attributes
|
|
|
The processor setup defines fixed attributes for the four processor-internal address space regions.
|
The processor setup defines fixed attributes for the four processor-internal address space regions.
|
Accessing a memory region in a way that violates any of these attributes will raise an according
|
Accessing a memory region in a way that violates any of these attributes will raise an according
|
access exception..
|
access exception..
|
|
|
* `r` – read access (from CPU data access interface, e.g. via "load")
|
* `r` - read access (from CPU data access interface, "loads")
|
* `w` – write access (from CPU data access interface, e.g. via "store")
|
* `w` - write access (from CPU data access interface, "stores")
|
* `x` – execute access (from CPU instruction fetch interface)
|
* `x` - execute access (from CPU instruction fetch interface)
|
* `a` – atomic access (from CPU data access interface)
|
* `a` - atomic access (from CPU data access interface)
|
* `8` – byte (8-bit)-accessible (when writing)
|
* `8` - byte (8-bit)-accessible (when writing)
|
* `16` – half-word (16-bit)-accessible (when writing)
|
* `16` - half-word (16-bit)-accessible (when writing)
|
* `32` – word (32-bit)-accessible (when writing)
|
* `32` - word (32-bit)-accessible (when writing)
|
|
|
[NOTE]
|
[NOTE]
|
Read accesses (i.e. loads) can always access data in word, half-word and byte quantities (requiring an accordingly aligned address).
|
Read accesses (loads and instruction fetches) can always access data in
|
|
word, half-word (for instruction fetch only if `C` extension is enabled)
|
|
and byte (not for instruction fetch) quantities (requiring an accordingly aligned address).
|
|
|
|
[TIP]
|
|
The following table shows the _default hardware-defined_ physical memory attributes of each main address space region.
|
|
Additional user-defined attributes (for example certain read/write/execute rights for specific address space regions) can be
|
|
provided using the RISC-V <<_machine_physical_memory_protection>>.
|
|
|
[cols="^1,^2,^2,^3,^2"]
|
[cols="^1,^2,^2,^3,^2"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| # | Region | Base address | Size | Attributes
|
| # | Region | Base address | Size | Attributes
|
| 4 | IO/peripheral devices | 0xfffffe00 | 512 bytes | `r/w/a/32`
|
| 5 | IO/peripheral devices | 0xfffffe00 | 512 bytes | `r/w/a/32`
|
| 3 | bootloader ROM | 0xffff0000 | up to 32kB| `r/x/a`
|
| 4 | On-chip debugger | 0xfffff800 | 512 bytes | `r/w/x/32`
|
| 2 | DMEM | 0x80000000 | up to 2GB (-64kB) | `r/w/x/a/8/16/32`
|
| 3 | Bootloader ROM | 0xffff0000 | up to 32kB | `r/x/a`
|
|
| 2 | DMEM | 0x80000000 | up to "2GB" | `r/w/x/a/8/16/32`
|
| 1 | IMEM | 0x00000000 | up to 2GB | `r/w/x/a/8/16/32`
|
| 1 | IMEM | 0x00000000 | up to 2GB | `r/w/x/a/8/16/32`
|
|=======================
|
|=======================
|
|
|
[TIP]
|
|
The following table shows the provided physical memory attributes of each region. Additional attributes (for example
|
|
controlling certain right for specific address space regions) can be provided using the RISC-V <<_machine_physical_memory_protection>> extension.
|
|
|
|
|
|
:sectnums:
|
:sectnums:
|
==== Memory Configuration
|
==== Memory Configuration
|
|
|
The NEORV32 Processor was designed to provide maximum flexibility for the memory configuration.
|
The NEORV32 Processor was designed to provide maximum flexibility for the memory configuration.
|
| Line 1261... |
Line 1317... |
memories, an external memory interface and a bus infrastructure to interconnect all units. Additionally, the
|
memories, an external memory interface and a bus infrastructure to interconnect all units. Additionally, the
|
system implements an internal reset generator and a global clock generator/divider.
|
system implements an internal reset generator and a global clock generator/divider.
|
|
|
**Internal Reset Generator**
|
**Internal Reset Generator**
|
|
|
Most processor-internal modules – except for the CPU and the watchdog timer – do not have a dedicated
|
Most processor-internal modules - except for the CPU and the watchdog timer - do not have a dedicated
|
reset signal. However, all devices can be reset by software by clearing the corresponding unit's control
|
reset signal. However, all devices can be reset by software by clearing the corresponding unit's control
|
register. The automatically included application start-up code (`crt0.S`) will perform a software-reset of all
|
register. The automatically included application start-up code (`crt0.S`) will perform a software-reset of all
|
modules to ensure a clean system reset state.
|
modules to ensure a clean system reset state.
|
|
|
The hardware reset signal of the processor can either be
|
The hardware reset signal of the processor can either be
|
