| Line 1055... |
Line 1055... |
| `mext_irq_i` | 1 | Machine external interrupt. This interrupt is used for any processor-external interrupt source (like a platform interrupt controller).
|
| `mext_irq_i` | 1 | Machine external interrupt. This interrupt is used for any processor-external interrupt source (like a platform interrupt controller).
|
|=======================
|
|=======================
|
|
|
.Trigger type
|
.Trigger type
|
[IMPORTANT]
|
[IMPORTANT]
|
The fast interrupt request channel trigger on **high-level** and have to stay asserted until explicitly acknowledged
|
The fast interrupt request channels become pending after being triggering by **a rising edge**. A pending FIRQ has to
|
by the software (for example by writing to a specific memory-mapped register). Hence, pending interrupts remain pending
|
be explicitly cleared by setting the according `mip` CSR bit.
|
as long as the interrupt-causing device's state fulfills it's interrupt condition(s).
|
|
|
|
|
|
:sectnums:
|
:sectnums:
|
==== Platform External Interrupts
|
==== Platform External Interrupts
|
|
|
| Line 1115... |
Line 1114... |
| 13:15 | - | _reserved_, will never fire
|
| 13:15 | - | _reserved_, will never fire
|
|=======================
|
|=======================
|
|
|
.Trigger type
|
.Trigger type
|
[IMPORTANT]
|
[IMPORTANT]
|
The fast interrupt request channel trigger on **high-level** and have to stay asserted until explicitly acknowledged
|
The fast interrupt request channels become pending after being triggering by **a rising edge**. A pending FIRQ has to
|
by the software (for example by writing to a specific memory-mapped register). Hence, pending interrupts remain pending
|
be explicitly cleared by setting the according `mip` CSR bit.
|
as long as the interrupt-causing device's state fulfills it's interrupt condition(s).
|
|
|
|
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
| Line 1422... |
Line 1420... |
You should use the provided core software library to interact with the peripheral devices. This
|
You should use the provided core software library to interact with the peripheral devices. This
|
prevents incompatibilities with future versions, since the hardware driver functions handle all the
|
prevents incompatibilities with future versions, since the hardware driver functions handle all the
|
register and register bit accesses.
|
register and register bit accesses.
|
|
|
[TIP]
|
[TIP]
|
|
A CMSIS-SVD-compatible **System View Description (SVD)** file including all peripherals is available in `sw/svd`.
|
|
|
|
[TIP]
|
Most of the IO devices do not have a hardware reset. Instead, the devices are reset via software by
|
Most of the IO devices do not have a hardware reset. Instead, the devices are reset via software by
|
writing zero to the unit's control register. A general software-based reset of all devices is done by the
|
writing zero to the unit's control register. A general software-based reset of all devices is done by the
|
application start-up code `crt0.S`.
|
application start-up code `crt0.S`.
|
|
|
**Interrupts of Processor-Internal Modules**
|
**Interrupts of Processor-Internal Modules**
|
