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|=======================
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|=======================
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**Theory of Operation**
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**Theory of Operation**
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The custom functions subsystem is meant for implementing custom and application-specific logic.
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The custom functions subsystem is meant for implementing custom and application-specific logic.
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The CFS provides up to 32x 32-bit memory-mapped
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The CFS provides up to 32x 32-bit memory-mapped read/write
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registers (`REG`, see register map below) that can be accessed by the CPU via normal load/store operations.
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registers (`REG`, see register map below) that can be accessed by the CPU via normal load/store operations.
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The actual functionality of these register has to be defined by the hardware designer. Furthermore, the CFS
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The actual functionality of these register has to be defined by the hardware designer. Furthermore, the CFS
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provides two IO conduits to implement custom module- or chip-external interfaces.
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provides two IO conduits to implement custom on-chip or off-chip interfaces.
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In contrast to connecting custom hardware accelerators via external memory interfaces (like SPI or the processor's
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In contrast to connecting custom hardware accelerators via external memory interfaces (like SPI or the processor's
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external bus interface), the CFS provide a convenient, low-latency and tightly-coupled extension and
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external bus interface), the CFS provide a convenient, low-latency and tightly-coupled extension and
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customization option.
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customization option.
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**CFS Software Access**
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**CFS Software Access**
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The CFS memory-mapped registers can be accessed by software using the provided C-language aliases (see
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The CFS memory-mapped registers can be accessed by software using the provided C-language aliases (see
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register map table below). Note that all interface registers provide 32-bit access data of type `uint32_t`.
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register map table below). Note that all interface registers are declared as 32-bit words of type `uint32_t`.
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.CFS Software Access Example
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[source,c]
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[source,c]
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----
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----
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// C-code CFS usage example
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// C-code CFS usage example
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NEORV32_CFS.REG[0] = (uint32_t)some_data_array(i); // write to CFS register 0
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NEORV32_CFS.REG[0] = (uint32_t)some_data_array(i); // write to CFS register 0
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uint32_t temp = NEORV32_CFS.REG[20]; // read from CFS register 20
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int temp = (int)NEORV32_CFS.REG[20]; // read from CFS register 20
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----
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----
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[TIP]
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[TIP]
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A very simple example program that uses the _default_ CFS hardware module can be found in `sw/example/cfs_demo`.
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A very simple example program that uses the _default_ CFS hardware module can be found in `sw/example/cfs_demo`.
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**CFS Interrupt**
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**CFS Interrupt**
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The CFS provides a single high-level-triggered interrupt request signal mapped to the CPU's fast interrupt channel 1.
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The CFS provides a single high-level-triggered interrupt request signal mapped to the CPU's fast interrupt channel 1.
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Once triggered, the interrupt becomes pending (if enabled in the `mis` CSR) and has to be explicitly cleared again by setting
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Once triggered, the interrupt becomes pending (if enabled in the `mis` CSR) and has to be explicitly cleared again by
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the according `mip` CSR bit. See section <<_processor_interrupts>> for more information.
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writing zero to the according <<_mip>> CSR bit. See section <<_processor_interrupts>> for more information.
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**CFS Configuration Generic**
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**CFS Configuration Generic**
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By default, the CFS provides a single 32-bit `std_(u)logic_vector` configuration generic _IO_CFS_CONFIG_
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By default, the CFS provides a single 32-bit `std_(u)logic_vector` configuration generic _IO_CFS_CONFIG_
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