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[/] [neorv32/] [trunk/] [docs/] [datasheet/] [soc_mtime.adoc] - Diff between revs 64 and 65
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[NOTE]
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[NOTE]
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If the processor-internal **MTIME unit is NOT implemented**, the top's `mtime_i` input signal is used to update the `time[h]` CSRs
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If the processor-internal **MTIME unit is NOT implemented**, the top's `mtime_i` input signal is used to update the `time[h]` CSRs
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and the `MTI` machine timer CPU interrupt (`MTI`) is directly connected to the top's `mtime_irq_i` input.
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and the `MTI` machine timer CPU interrupt (`MTI`) is directly connected to the top's `mtime_irq_i` input.
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The 64-bit system time can be accessed via the `TIME_LO` and `TIME_HI` memory-mapped registers (read/write) and also via
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The 64-bit system time can be accessed via the `TIME_LO` and `TIME_HI` memory-mapped registers (read/write) and also via
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the CPU's `time[h]` CSRs (read-only). A 64-bit time compare register – accessible via memory-mapped `TIMECMP_LO` and `TIMECMP_HI`
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the CPU's `time[h]` CSRs (read-only). A 64-bit time compare register - accessible via memory-mapped `TIMECMP_LO` and `TIMECMP_HI`
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registers – is used to configure an interrupt to the CPU. The interrupt is triggered
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registers - is used to configure an interrupt to the CPU. The interrupt is triggered
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whenever `TIME` (high & low part) >= `TIMECMP` (high & low part) and is directly forwarded to the CPU's `MTI` interrupt.
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whenever `TIME` (high & low part) >= `TIMECMP` (high & low part) and is directly forwarded to the CPU's `MTI` interrupt.
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The interrupt remain active (=pending) until `TIME` < `TIMECMP` (either by modifying `TIME` or `TIMECMP`).
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.MTIME register map (`struct NEORV32_MTIME`)
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.MTIME register map (`struct NEORV32_MTIME`)
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[cols="<3,<3,^1,^1,<6"]
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[cols="<3,<3,^1,^1,<6"]
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[options="header",grid="all"]
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[options="header",grid="all"]
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