| Line 28... |
Line 28... |
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The interface provides a single 1-bit output `neoled_o` to drive an arbitrary number of cascaded LEDs. Since the
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The interface provides a single 1-bit output `neoled_o` to drive an arbitrary number of cascaded LEDs. Since the
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NEOLED module provides 24-bit and 32-bit operating modes, a mixed setup with RGB LEDs (24-bit color)
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NEOLED module provides 24-bit and 32-bit operating modes, a mixed setup with RGB LEDs (24-bit color)
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and RGBW LEDs (32-bit color including a dedicated white LED chip) is possible.
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and RGBW LEDs (32-bit color including a dedicated white LED chip) is possible.
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**Theory of Operation – NEOLED Module**
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**Theory of Operation - NEOLED Module**
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The NEOLED modules provides two accessible interface registers: the control register `CTRL` and the
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The NEOLED modules provides two accessible interface registers: the control register `CTRL` and the
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TX data register `DATA`. The NEOLED module is globally enabled via the control register's
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TX data register `DATA`. The NEOLED module is globally enabled via the control register's
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_NEOLED_CTRL_EN_ bit. Clearing this bit will terminate any current operation, clear the TX buffer, reset the module
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_NEOLED_CTRL_EN_ bit. Clearing this bit will terminate any current operation, clear the TX buffer, reset the module
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and set the `neoled_o` output to zero. The precise timing (implementing the **WS2812** protocol) and transmission
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and set the `neoled_o` output to zero. The precise timing (implementing the **WS2812** protocol) and transmission
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| Line 53... |
Line 53... |
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The mode bit can be configured before writing each new data word in order to support
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The mode bit can be configured before writing each new data word in order to support
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an arbitrary setup of RGB and RGBW LEDs.
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an arbitrary setup of RGB and RGBW LEDs.
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**Theory of Operation – Protocol**
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**Theory of Operation - Protocol**
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The interface of the WS2812 LEDs uses an 800kHz carrier signal. Data is transmitted in a serial manner
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The interface of the WS2812 LEDs uses an 800kHz carrier signal. Data is transmitted in a serial manner
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starting with LSB-first. The intensity for each R, G & B (& W) LED chip (= color code) is defined via an 8-bit
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starting with LSB-first. The intensity for each R, G & B (& W) LED chip (= color code) is defined via an 8-bit
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value. The actual data bits are transferred by modifying the duty cycle of the signal (the timings for the
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value. The actual data bits are transferred by modifying the duty cycle of the signal (the timings for the
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WS2812 are shown below). A RESET command is "send" by pulling the data line LOW for at least 50μs.
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WS2812 are shown below). A RESET command is "send" by pulling the data line LOW for at least 50μs.
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| Line 95... |
Line 95... |
defined via the 5-bit _NEOLED_CTRL_T_ONE_H_x_ and _NEOLED_CTRL_T_ZERO_H_x_ values, respectively. These programmable
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defined via the 5-bit _NEOLED_CTRL_T_ONE_H_x_ and _NEOLED_CTRL_T_ZERO_H_x_ values, respectively. These programmable
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timing constants allow to adapt the interface for a wide variety of smart LED protocol (for example WS2812 vs.
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timing constants allow to adapt the interface for a wide variety of smart LED protocol (for example WS2812 vs.
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WS2811).
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WS2811).
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**Timing Configuration – Example (WS2812)**
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**Timing Configuration - Example (WS2812)**
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Generate the base clock f~TX~ for the NEOLED TX engine:
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Generate the base clock f~TX~ for the NEOLED TX engine:
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* processor clock f~main~ = 100 MHz
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* processor clock f~main~ = 100 MHz
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* _NEOLED_CTRL_PRSCx_ = `0b001` = f~main~ / 4
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* _NEOLED_CTRL_PRSCx_ = `0b001` = f~main~ / 4
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| Line 157... |
Line 157... |
To circumvent this, the NEOLED module provides an option to automatically issue an idle time for creating the RESET
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To circumvent this, the NEOLED module provides an option to automatically issue an idle time for creating the RESET
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command. If the _NEOLED_CTRL_STROBE_ control register bit is set, _all_ data written to the data FIFO (via `DATA`,
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command. If the _NEOLED_CTRL_STROBE_ control register bit is set, _all_ data written to the data FIFO (via `DATA`,
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the actually written data is irrelevant) will trigger an idle phase (`neoled_o` = zero) of 127 periods (= _**T~carrier~**_).
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the actually written data is irrelevant) will trigger an idle phase (`neoled_o` = zero) of 127 periods (= _**T~carrier~**_).
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This idle time will cause the LEDs to strobe the color data into the PWM driver registers.
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This idle time will cause the LEDs to strobe the color data into the PWM driver registers.
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Since the _NEOLED_CTRL_STROBE_ flag is also buffered in the TX buffer, the RESET command is treated as just another
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Since the _NEOLED_CTRL_STROBE_ flag is also buffered in the TX buffer, the RESET command is treated just as another
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data word being written to the TX buffer making busy wait concepts obsolete and allowing maximum refresh rates.
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data word being written to the TX buffer making busy wait concepts obsolete and allowing maximum refresh rates.
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**Interrupt**
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**Interrupt**
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The NEOLED modules features a single interrupt that is triggered whenever the TX FIFO's fill level
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The NEOLED modules features a single interrupt that becomes pending based on the current TX buffer fill level.
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falls below _half-full_ level. In this case software can write up to _IO_NEOLED_TX_FIFO_/2 new data
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The interrupt can only become pending if the NEOLED module is enabled. The specific interrupt condition
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words to `DATA` without checking the FIFO status flags.
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is configured via the _NEOLED_CTRL_IRQ_CONF_ in the control register `NEORV32_NEOLED.CTRL`.
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If _NEOLED_CTRL_IRQ_CONF_ is cleared, an interrupt is generated whenever the TX FIFO is _less than half-full_.
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In this case software can write up to _IO_NEOLED_TX_FIFO_/2 new data words to `DATA` without checking the FIFO
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status flags. The interrupt request is cleared whenever the FIFO fill level is above _half-full_ level or if
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the NEOLED module is disabled.
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This highly relaxes time constraints for sending a continuous data stream to the LEDs
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If _NEOLED_CTRL_IRQ_CONF_ is set, an interrupt is generated whenever the TX FIFO is _empty_. The interrupt
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(as an idle time beyond 50μs will trigger the LED's a RESET command).
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request is cleared again when the FIFO contains at least one data word.
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[NOTE]
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The _NEOLED_CTRL_IRQ_CONF_ is hardwired to one if _IO_NEOLED_TX_FIFO_ = 1 (-> IRQ if FIFO is empty).
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If the FIFO is configured to contain only a single entry (_IO_NEOLED_TX_FIFO_ = 1) the interrupt
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will become pending if the FIFO (which is just a single register providing simple _double-buffering_) is empty.
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.NEOLED register map (`struct NEORV32_NEOLED`)
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.NEOLED register map (`struct NEORV32_NEOLED`)
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[cols="<4,<5,<9,^2,<9"]
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[cols="<4,<5,<9,^2,<9"]
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[options="header",grid="all"]
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[options="header",grid="all"]
|
|=======================
|
|=======================
|
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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.25+<| `0xffffffd8` .25+<| `NEORV32_NEOLED.CTRL` <|`0` _NEOLED_CTRL_EN_ ^| r/w <| NEOLED enable
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.30+<| `0xffffffd8` .30+<| `NEORV32_NEOLED.CTRL` <|`0` _NEOLED_CTRL_EN_ ^| r/w <| NEOLED enable
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<|`1` _NEOLED_CTRL_MODE_ ^| r/w <| data transfer size; `0`=24-bit; `1`=32-bit
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<|`1` _NEOLED_CTRL_MODE_ ^| r/w <| data transfer size; `0`=24-bit; `1`=32-bit
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<|`2` _NEOLED_CTRL_STROBE_ ^| r/w <| `0`=send normal color data; `1`=send RESET command on data write access
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<|`2` _NEOLED_CTRL_STROBE_ ^| r/w <| `0`=send normal color data; `1`=send RESET command on data write access
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<|`3` _NEOLED_CTRL_PRSC0_ ^| r/w <| 3-bit clock prescaler, bit 0
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<|`3` _NEOLED_CTRL_PRSC0_ ^| r/w <| 3-bit clock prescaler, bit 0
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<|`4` _NEOLED_CTRL_PRSC1_ ^| r/w <| 3-bit clock prescaler, bit 1
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<|`4` _NEOLED_CTRL_PRSC1_ ^| r/w <| 3-bit clock prescaler, bit 1
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<|`5` _NEOLED_CTRL_PRSC2_ ^| r/w <| 3-bit clock prescaler, bit 2
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<|`5` _NEOLED_CTRL_PRSC2_ ^| r/w <| 3-bit clock prescaler, bit 2
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| Line 192... |
Line 203... |
<|`10` _NEOLED_CTRL_T_TOT_0_ ^| r/w .5+<| 5-bit pulse clock ticks per total single-bit period (T~total~)
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<|`10` _NEOLED_CTRL_T_TOT_0_ ^| r/w .5+<| 5-bit pulse clock ticks per total single-bit period (T~total~)
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<|`11` _NEOLED_CTRL_T_TOT_1_ ^| r/w
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<|`11` _NEOLED_CTRL_T_TOT_1_ ^| r/w
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<|`12` _NEOLED_CTRL_T_TOT_2_ ^| r/w
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<|`12` _NEOLED_CTRL_T_TOT_2_ ^| r/w
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<|`13` _NEOLED_CTRL_T_TOT_3_ ^| r/w
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<|`13` _NEOLED_CTRL_T_TOT_3_ ^| r/w
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<|`14` _NEOLED_CTRL_T_TOT_4_ ^| r/w
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<|`14` _NEOLED_CTRL_T_TOT_4_ ^| r/w
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<|`20` _NEOLED_CTRL_ONE_H_0_ ^| r/w .5+<| 5-bit pulse clock ticks per high-time for sending a one-bit (T~H1~)
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<|`15` _NEOLED_CTRL_T_ZERO_H_0_ ^| r/w .5+<| 5-bit pulse clock ticks per high-time for sending a zero-bit (T~0H~)
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<|`21` _NEOLED_CTRL_ONE_H_1_ ^| r/w
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<|`16` _NEOLED_CTRL_T_ZERO_H_1_ ^| r/w
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<|`22` _NEOLED_CTRL_ONE_H_2_ ^| r/w
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<|`17` _NEOLED_CTRL_T_ZERO_H_2_ ^| r/w
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<|`23` _NEOLED_CTRL_ONE_H_3_ ^| r/w
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<|`18` _NEOLED_CTRL_T_ZERO_H_3_ ^| r/w
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<|`24` _NEOLED_CTRL_ONE_H_4_ ^| r/w
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<|`19` _NEOLED_CTRL_T_ZERO_H_4_ ^| r/w
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<|`30` _NEOLED_CTRL_TX_STATUS_ ^| r/- <| transmit engine busy when `1`
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<|`20` _NEOLED_CTRL_T_ONE_H_0_ ^| r/w .5+<| 5-bit pulse clock ticks per high-time for sending a one-bit (T~1H~)
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<|`31` _NEOLED_CTRL_TX_EMPTY_ ^| r/- <| TX FIFO is empty
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<|`21` _NEOLED_CTRL_T_ONE_H_1_ ^| r/w
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<|`31` _NEOLED_CTRL_TX_HALF_ ^| r/- <| TX FIFO is _at least_ half full
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<|`22` _NEOLED_CTRL_T_ONE_H_2_ ^| r/w
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<|`31` _NEOLED_CTRL_TX_FULL_ ^| r/- <| TX FIFO is full
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<|`23` _NEOLED_CTRL_T_ONE_H_3_ ^| r/w
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<|`24` _NEOLED_CTRL_T_ONE_H_4_ ^| r/w
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<|`27` _NEOLED_CTRL_IRQ_CONF_ ^| r/w <| TX FIFO interrupt configuration: `0`=IRQ if FIFO is less than half-full, `1`=IRQ if FIFO is empty
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<|`28` _NEOLED_CTRL_TX_EMPTY_ ^| r/- <| TX FIFO is empty
|
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<|`29` _NEOLED_CTRL_TX_HALF_ ^| r/- <| TX FIFO is _at least_ half full
|
|
<|`30` _NEOLED_CTRL_TX_FULL_ ^| r/- <| TX FIFO is full
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<|`31` _NEOLED_CTRL_TX_BUSY_ ^| r/- <| TX serial engine is busy when set
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<|`31` _NEOLED_CTRL_TX_BUSY_ ^| r/- <| TX serial engine is busy when set
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| `0xffffffdc` | `NEORV32_NEOLED.DATA` <|`31:0` / `23:0` ^| -/w <| TX data (32-/24-bit)
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| `0xffffffdc` | `NEORV32_NEOLED.DATA` <|`31:0` / `23:0` ^| -/w <| TX data (32-/24-bit)
|
|=======================
|
|=======================
|
