| Line 42... |
Line 42... |
The SLINK interface does not provide any additional tag signals (for example to define a "stream destination
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The SLINK interface does not provide any additional tag signals (for example to define a "stream destination
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address" or to indicate the last data word of a "package"). Use a custom controller connected
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address" or to indicate the last data word of a "package"). Use a custom controller connected
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via the external memory bus interface or use some of the processor's GPIO ports to implement custom data
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via the external memory bus interface or use some of the processor's GPIO ports to implement custom data
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tag signals.
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tag signals.
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**Theory of Operation**
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**Theory of Operation**
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The SLINK provides eight data registers (`DATA[i]`) to access the links (read accesses will access the RX links, write
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The SLINK provides eight data registers (`DATA[i]`) to access the links (read accesses will access the RX links, write
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accesses will access the TX links), one control register (`CTRL`) and one status register (`STATUS`).
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accesses will access the TX links), one control register (`CTRL`) and one status register (`STATUS`).
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| Line 80... |
Line 81... |
Hence, blocking access to a stream link that does not complete within a certain amount of cycles will
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Hence, blocking access to a stream link that does not complete within a certain amount of cycles will
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raise a _store bus access exception_ when writing a _full_ TX link or a _load bus access exception_ when reading
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raise a _store bus access exception_ when writing a _full_ TX link or a _load bus access exception_ when reading
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from an _empty_ RX link. Hence, this concept should only be used when evaluating the half-full FIFO condition
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from an _empty_ RX link. Hence, this concept should only be used when evaluating the half-full FIFO condition
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(for example via the SLINK interrupts) before actual accessing links.
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(for example via the SLINK interrupts) before actual accessing links.
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**Non-Blocking Link Access**
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**Non-Blocking Link Access**
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For a non-blocking link access concept, the FIFO status flags in `STATUS` need to be checked _before_
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For a non-blocking link access concept, the FIFO status flags in `STATUS` need to be checked _before_
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reading/writing the actual link data register. For example, a non-blocking write access to a TX link 0 has
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reading/writing the actual link data register. For example, a non-blocking write access to a TX link 0 has
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to check _SLINK_STATUS_TX0_FREE_ first. If the bit is set, the FIFO of TX link 0 can take another data word
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to check _SLINK_STATUS_TX0_FREE_ first. If the bit is set, the FIFO of TX link 0 can take another data word
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| Line 92... |
Line 94... |
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This concept will not raise any exception as there is no "direct" access to the link data registers.
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This concept will not raise any exception as there is no "direct" access to the link data registers.
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However, non-blocking accesses require additional instructions to check the according status flags prior
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However, non-blocking accesses require additional instructions to check the according status flags prior
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to the actual link access, which will reduce performance for high-bandwidth data streams.
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to the actual link access, which will reduce performance for high-bandwidth data streams.
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**Interrupts**
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The stream interface provides two interrupts that are _globally_ driven by the RX and TX link's
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FIFO fill level status. The behavior of these interrupts differs if the FIFO depth is exactly 1 (minimal)
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or if it is greater than 1.
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When _SLINK_*X_FIFO_ is 1 a TX interrupt will fire if **any** TX link _was full_ and _becomes empty_ again.
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Accordingly, if the FIFO of **any** RX link _was empty_ and a _new data word_ appears in it, the RX interrupt fires.
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When _SLINK_*X_FIFO_ is greater than 1 the TX interrupt will fire if _any_ TX link's FIFO _falls below_ half-full fill level.
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Accordingly, the RX interrupt will fire if _any_ RX link's FIFO _exceeds_ half-full fill level.
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The interrupt service handler has to evaluate the SLINK status register is order to detect which link(s) has caused the
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interrupt. No further interrupt can fire until the CPU acknowledges the last interrupt by _reading the SLINK status register_.
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However, further IRQ conditions are buffered and will trigger another interrupt after the current one has been acknowledged.
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Note that these interrupts can only fire if the SLINK module is actually enabled by setting the
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_SLINK_CTRL_EN_ bit in the unit's control register.
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**Stream Link Interface & Protocol**
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**Stream Link Interface & Protocol**
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The SLINK interface consists of three signals `dat`, `val` and `rdy` for each RX and TX link.
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The SLINK interface consists of three signals `dat`, `val` and `rdy` for each RX and TX link.
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Each signal is an "array" with eight entires (one for each link). Note that an entry in `slink_*x_dat` is 32-bit
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Each signal is an "array" with eight entires (one for each link). Note that an entry in `slink_*x_dat` is 32-bit
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| Line 131... |
Line 115... |
image::stream_link_interface.png[width=560,align=center]
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image::stream_link_interface.png[width=560,align=center]
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[TIP]
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[TIP]
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The SLINK handshake protocol is compatible with the https://developer.arm.com/documentation/ihi0051/a/Introduction/About-the-AXI4-Stream-protocol[AXI4-Stream] base protocol.
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The SLINK handshake protocol is compatible with the https://developer.arm.com/documentation/ihi0051/a/Introduction/About-the-AXI4-Stream-protocol[AXI4-Stream] base protocol.
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**Interrupts**
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The stream interface provides two independent interrupts that are _globally_ driven by the RX and TX link's
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FIFO fill level status. Each RX and TX link provides an individual interrupt enable flag and an individual
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interrupt type flag that allows to configure interrupts only for certain (or all) links and for application-
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specific interrupt conditions. The interrupt configuration is done using the `NEORV32_SLINK.IRQ` register.
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Any interrupt can only become pending if the SLINK module is enabled at all.
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The current FIFO fill-level of a specific **RX link** can only raise an interrupt request if it's interrupt enable flag
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_SLINK_IRQ_RX_EN_ is set. Vice versa, the current FIFO fill-level of a specific **TX link** can only raise an interrupt
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request if it's interrupt enable flag _SLINK_IRQ_TX_EN_ is set.
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The **RX link's** _SLINK_IRQ_RX_MODE_ flags define the FIFO fill-level condition for raising an RX interrupt request:
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* If a link's interrupt mode flag is `1` an IRQ is generated when the link's FIFO is _not empty_ ("RX data available").
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* If a link's interrupt mode flag is `0` an IRQ is generated when the link's FIFO is _at least half-full_ ("time to get data from RX FIFO to prevent overflow").
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The **TX link's** _SLINK_IRQ_TX_MODE_ flags define the FIFO fill-level condition for raising an TX interrupt request:
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* If a link's interrupt mode flag is `1` an IRQ is generated when the link's FIFO is _not full_ ("space left in FIFO for new TX data").
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* If a link's interrupt mode flag is `0` an IRQ is generated when the link's FIFO is _less than half-full_ ("SW can send _SLINK_TX_FIFO_/2 data words without checking any flags").
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[NOTE]
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If _SLINK_RX_FIFO_ is 1 the _SLINK_IRQ_RX_MODE_ bits are hardwired to one.
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If _SLINK_TX_FIFO_ is 1 the _SLINK_IRQ_TX_MODE_ bits are hardwired to one.
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[NOTE]
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There is no RX FIFO overflow mechanism available yet.
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If _any_ configured interrupt condition is fulfilled, the according global SLINK RX / SLINK TX CPU
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interrupt becomes pending.
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If the interrupt enable flags of several links are set, the interrupt service handler has to evaluate the SLINK
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status register is order to detect which link(s) caused the interrupt.
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[NOTE]
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If the programmed interrupt condition is fulfilled, the corresponding IRQ will become _pending_ until
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the causing interrupt conditions is resolved (for example by reading data from the according RX FIFO).
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.SLINK register map (`struct NEORV32_SLINK`)
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.SLINK register map (`struct NEORV32_SLINK`)
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[cols="^4,<5,^2,^2,<14"]
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[cols="^4,<5,^2,^2,<14"]
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[options="header",grid="all"]
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[options="header",grid="all"]
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|=======================
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|=======================
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| Address | Name [C] | Bit(s) | R/W | Function
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| Address | Name [C] | Bit(s) | R/W | Function
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| Line 142... |
Line 164... |
<| `30:16` _reserved_ ^| r/- <| reserved, read as zero
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<| `30:16` _reserved_ ^| r/- <| reserved, read as zero
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<| `15:12` _SLINK_CTRL_TX_FIFO_S3_ : _SLINK_CTRL_TX_FIFO_S0_ ^| r/- <| TX links FIFO depth, log2 of_SLINK_TX_FIFO_ generic
|
<| `15:12` _SLINK_CTRL_TX_FIFO_S3_ : _SLINK_CTRL_TX_FIFO_S0_ ^| r/- <| TX links FIFO depth, log2 of_SLINK_TX_FIFO_ generic
|
<| `11:8` _SLINK_CTRL_RX_FIFO_S3_ : _SLINK_CTRL_RX_FIFO_S0_ ^| r/- <| RX links FIFO depth, log2 of_SLINK_RX_FIFO_ generic
|
<| `11:8` _SLINK_CTRL_RX_FIFO_S3_ : _SLINK_CTRL_RX_FIFO_S0_ ^| r/- <| RX links FIFO depth, log2 of_SLINK_RX_FIFO_ generic
|
<| `7:4` _SLINK_CTRL_TX_NUM3_ : _SLINK_CTRL_TX_NUM0_ ^| r/- <| Number of implemented TX links
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<| `7:4` _SLINK_CTRL_TX_NUM3_ : _SLINK_CTRL_TX_NUM0_ ^| r/- <| Number of implemented TX links
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<| `3:0` _SLINK_CTRL_RX_NUM3_ : _SLINK_CTRL_RX_NUM0_ ^| r/- <| Number of implemented RX links
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<| `3:0` _SLINK_CTRL_RX_NUM3_ : _SLINK_CTRL_RX_NUM0_ ^| r/- <| Number of implemented RX links
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| `0xfffffec4` : `0xfffffeec` | - |`31:0` | | _reserved
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| `0xfffffec4` | - |`31:0` | r/- | _reserved_
|
.4+<| `0xfffffed0` .4+<| `NEORV32_SLINK.STATUS` <| `31:24` _SLINK_STATUS_TX7_HALF_ : _SLINK_STATUS_TX0_HALF_ ^| r/- | TX link 7..0 FIFO fill level is > half-full
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.4+<| `0xfffffec8` .4+<| `NEORV32_SLINK.IRQ` <|`31:24` _SLINK_IRQ_RX_EN_MSB_ : _SLINK_IRQ_RX_EN_LSB_ ^| r/w <| RX interrupt enable for link 7..0
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<|`23:16` _SLINK_IRQ_RX_MODE_MSB_ : _SLINK_IRQ_RX_MODE_LSB_ ^| r/w <| RX IRQ mode for link 7..0: `0` = FIFO at least half-full; `1` = FIFO not empty
|
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<|`15:8` _SLINK_IRQ_TX_EN_MSB_ : _SLINK_IRQ_TX_EN_LSB_ ^| r/w <| TX interrupt enable for link 7..0
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<|`7:0` _SLINK_IRQ_TX_MODE_MSB_ : _SLINK_IRQ_TX_MODE_LSB_ ^| r/w <| TX IRQ mode for link 7..0: `0` = FIFO less than half-full; `1` = FIFO not full
|
|
| `0xfffffeec` | - |`31:0` | r/- | _reserved_
|
|
.4+<| `0xfffffed0` .4+<| `NEORV32_SLINK.STATUS` <| `31:24` _SLINK_STATUS_TX7_HALF_ : _SLINK_STATUS_TX0_HALF_ ^| r/- <| TX link 7..0 FIFO fill level is >= half-full
|
<| `23:16` _SLINK_STATUS_RX7_HALF_ : _SLINK_STATUS_RX0_HALF_ ^| r/- <| RX link 7..0 FIFO fill level is >= half-full
|
<| `23:16` _SLINK_STATUS_RX7_HALF_ : _SLINK_STATUS_RX0_HALF_ ^| r/- <| RX link 7..0 FIFO fill level is >= half-full
|
<| `15:8` _SLINK_STATUS_TX7_FREE_ : _SLINK_STATUS_TX0_FREE_ ^| r/- <| At least one free TX FIFO entry available for link 7..0
|
<| `15:8` _SLINK_STATUS_TX7_FREE_ : _SLINK_STATUS_TX0_FREE_ ^| r/- <| At least one free TX FIFO entry available for link 7..0
|
<| `7:0` _SLINK_STATUS_RX7_AVAIL_ : _SLINK_STATUS_RX0_AVAIL_ ^| r/- <| At least one data word in RX FIFO available for link 7..0
|
<| `7:0` _SLINK_STATUS_RX7_AVAIL_ : _SLINK_STATUS_RX0_AVAIL_ ^| r/- <| At least one data word in RX FIFO available for link 7..0
|
| `0xfffffed4` : `0xfffffedc` | - |`31:0` | | _reserved_
|
| `0xfffffed4` : `0xfffffedc` | - |`31:0` | r/- | _reserved_
|
| `0xfffffee0` | `NEORV32_SLINK.DATA[0]` | `31:0` | r/w | Link 0 RX/TX data
|
| `0xfffffee0` | `NEORV32_SLINK.DATA[0]` | `31:0` | r/w | Link 0 RX/TX data
|
| `0xfffffee4` | `NEORV32_SLINK.DATA[1]` | `31:0` | r/w | Link 1 RX/TX data
|
| `0xfffffee4` | `NEORV32_SLINK.DATA[1]` | `31:0` | r/w | Link 1 RX/TX data
|
| `0xfffffee8` | `NEORV32_SLINK.DATA[2]` | `31:0` | r/w | Link 2 RX/TX data
|
| `0xfffffee8` | `NEORV32_SLINK.DATA[2]` | `31:0` | r/w | Link 2 RX/TX data
|
| `0xfffffeec` | `NEORV32_SLINK.DATA[3]` | `31:0` | r/w | Link 3 RX/TX data
|
| `0xfffffeec` | `NEORV32_SLINK.DATA[3]` | `31:0` | r/w | Link 3 RX/TX data
|
| `0xfffffef0` | `NEORV32_SLINK.DATA[4]` | `31:0` | r/w | Link 4 RX/TX data
|
| `0xfffffef0` | `NEORV32_SLINK.DATA[4]` | `31:0` | r/w | Link 4 RX/TX data
|
