URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 60 |
Rev 61 |
Line 76... |
Line 76... |
.TRNG register map
|
.TRNG register map
|
[cols="<2,<2,<4,^1,<7"]
|
[cols="<2,<2,<4,^1,<7"]
|
[options="header",grid="all"]
|
[options="header",grid="all"]
|
|=======================
|
|=======================
|
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
|
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
|
.3+<| `0xffffff88` .3+<| _TRNG_CT_ <|`7:0` _TRNG_CT_DATA_MSB_ : _TRNG_CT_DATA_MSB_ ^| r/- <| 8-bit random data output
|
.3+<| `0xffffffb8` .3+<| _TRNG_CT_ <|`7:0` _TRNG_CT_DATA_MSB_ : _TRNG_CT_DATA_MSB_ ^| r/- <| 8-bit random data output
|
<|`30` _TRNG_CT_EN_ ^| r/w <| TRNG enable
|
<|`30` _TRNG_CT_EN_ ^| r/w <| TRNG enable
|
<|`31` _TRNG_CT_VALID_ ^| r/- <| random data output is valid when set
|
<|`31` _TRNG_CT_VALID_ ^| r/- <| random data output is valid when set
|
|=======================
|
|=======================
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.