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| CPU interrupts:          | fast IRQ channel 2 | RX done interrupt

|                          | _UART0_RX_FIFO_ | RX FIFO depth (power of 2, min 1)

|                          | fast IRQ channel 3 | TX done interrupt (see <<_processor_interrupts>>)

|                          | _UART0_TX_FIFO_ | TX FIFO depth (power of 2, min 1)

|=======================

| CPU interrupts:          | fast IRQ channel 2 | RX interrupt

[IMPORTANT]

[NOTE]

(_UART0_) as default user console interface. For compatibility, all C-language function calls to

(_UART0_) as default user console interface.

`neorv32_uart_*` are mapped to the according primary UART (_UART0_) `neorv32_uart0_*`

In most cases, the UART is a standard interface used to establish a communication channel between the

UART0 is enabled by setting the _UART_CTRL_EN_ bit in the UART0 control register `CTRL`. The Baudrate

computer/user and an application running on the processor platform. The NEORV32 UARTs features a

is configured via a 12-bit _UART_CTRL_BAUDxx_ baud prescaler (`baud_prsc`) and a 3-bit _UART_CTRL_PRSCx_

standard configuration frame configuration: 8 data bits, an optional parity bit (even or odd) and 1 stop bit.

clock prescaler (`clock_prescaler`) that scales the processor's primary clock (_f~main~_).

.UART prescaler configuration

.UART0 prescaler configuration

_**Baudrate**_ = (_f~main~[Hz]_ / `clock_prescaler`) / (`baud_rate` + 1)

_**Baudrate**_ = (_f~main~[Hz]_ / `clock_prescaler`) / (`baud_prsc` + 1)

is available when the _UART_DATA_AVAIL_ flag of the UART0_DATA register is set. A "frame error" in a received byte

is available when the _UART_DATA_AVAIL_ flag of the `DATA` register is set. A "frame error" in a received byte

(broken stop bit) is indicated via the _UART_DATA_FERR_ flag in the UART0_DATA register.

(invalid stop bit) is indicated via the _UART_DATA_FERR_ flag in the `DATA` register. The flag is cleared by

The UART receive engine provides a simple data buffer with two entries. These two entries are transparent

**RX and TX FIFOs**

**Parity Modes**

UART0 provides optional FIFO buffers for the transmitter and the receiver. The _UART0_RX_FIFO_ generic defines

The parity flag is added if the _UART_CTRL_PMODE1_ flag is set. When _UART_CTRL_PMODE0_ is zero the UART

The state of both FIFO (_empty_, _at lest half-full_, _full_) is available via the _UART_CTRL_?X_EMPTY_,

operates in "even parity" mode. If this flag is set, the UART operates in "odd parity" mode. Parity errors in

 _UART_CTRL_?X_HALF_ and _UART_CTRL_*X_FULL_ flags in the `CTRL` register.

The RTS line is de-asserted (going high) as soon as the start bit of a new incoming char has been

If the RX FIFO is already full and new data is received by the receiver unit, the _UART_DATA_OVERR_ flag

detected. The transmitting device continues sending the current char and can also send another char

in the `DATA` register is set indicating an "overrun". This flag is cleared by reading the `DATA` register.

Signal changes on `uart0_cts_i` during an active transmission are ignored. Application software can check

[TIP]

Please note that – just like the RXD and TXD signals – the RTS and CTS signals have to be **cross**-coupled

**Parity Modes**

between devices.

The UART features two interrupts: the "TX done interrupt" is triggered when a transmit operation (sending) has finished. The "RX

UART0 features two independent interrupt for signaling certain RX and TX conditions. The behavior of these interrupts differ

done interrupt" is triggered when a data byte has been received. If the UART0 is not implemented, the UART0 interrupts are permanently tied to zero.

based on the configured FIFO size. If the according FIFO size is greater than 1, the _UART_CTRL_RX_IRQ_ and _UART_CTRL_TX_IRQ_

the defined baud rate. Even though the default testbench provides a simulated UART0 receiver, which

the defined baud rate via the physical link. To accelerate UART0 output during simulation

outputs any received char to the simulator console, such a transmission takes a lot of time. To accelerate

(and also to dump large amounts of data) the UART0 features a _simulation mode_.

If the UART is configured for simulation mode there will be **NO physical UART0 transmissions via

Simulation mode is enabled by setting the _UART_CTRL_SIM_MODE_ bit in the UART0's control register

`uart0_txd_o`** at all. Furthermore, no interrupts (RX done or TX done) will be triggered in any situation.

`CTRL`. Any other UART0 configuration bits are irrelevant for this mode but UART0 has to be enabled via the

More information regarding the simulation-mode of the UART0 can be found in the Uer Guide

More information regarding the simulation-mode of the UART0 can be found in the User Guide

.12+<| `0xffffffa0` .12+<| `NEORV32_UART0.CTRL` <|`11:0` _UART_CT_BAUDxx_ ^| r/w <| 12-bit BAUD value configuration value

.21+<| `0xffffffa0` .21+<| `NEORV32_UART0.CTRL` <|`11:0` _UART_CTRL_BAUDxx_ ^| r/w <| 12-bit BAUD value configuration value

                                                <|`12` _UART_CT_SIM_MODE_ ^| r/w <| enable **simulation mode**

                                                <|`12` _UART_CTRL_SIM_MODE_ ^| r/w <| enable **simulation mode**

                                                <|`20` _UART_CT_RTS_EN_   ^| r/w <| enable RTS hardware flow control

                                                <|`13` _UART_CTRL_RX_EMPTY_ ^| r/- <| RX FIFO is empty

                                                <|`21` _UART_CT_CTS_EN_   ^| r/w <| enable CTS hardware flow control

                                                <|`14` _UART_CTRL_RX_HALF_  ^| r/- <| RX FIFO is at least half-full

                                                <|`22` _UART_CT_PMODE0_   ^| r/w .2+<| parity bit enable and configuration (`00`/`01`= no parity; `10`=even parity; `11`=odd parity)

                                                <|`15` _UART_CTRL_RX_FULL_  ^| r/- <| RX FIFO is full

                                                <|`23` _UART_CT_PMODE1_   ^| r/w

                                                <|`16` _UART_CTRL_TX_EMPTY_ ^| r/- <| TX FIFO is empty

                                                <|`24` _UART_CT_PRSC0_    ^| r/w .3+<| 3-bit baudrate clock prescaler select

                                                <|`17` _UART_CTRL_TX_HALF_  ^| r/- <| TX FIFO is at least half-full

                                                <|`25` _UART_CT_PRSC1_    ^| r/w

                                                <|`18` _UART_CTRL_TX_FULL_  ^| r/- <| TX FIFO is full

                                                <|`26` _UART_CT_PRSC2_    ^| r/w

                                                <|`19` -                    ^| r/- <| _reserved_, read as zero

                                                <|`27` _UART_CT_CTS_      ^| r/- <| current state of UART's CTS input signal

                                                <|`20` _UART_CTRL_RTS_EN_   ^| r/w <| enable RTS hardware flow control

                                                <|`28` _UART_CT_EN_       ^| r/w <| UART enable

                                                <|`21` _UART_CTRL_CTS_EN_   ^| r/w <| enable CTS hardware flow control

                                                <|`31` _UART_CT_TX_BUSY_  ^| r/- <| trasmitter busy flag

                                                <|`22` _UART_CTRL_PMODE0_   ^| r/w .2+<| parity bit enable and configuration (`00`/`01`= no parity; `10`=even parity; `11`=odd parity)

| CPU interrupts:          | fast IRQ channel 4 | RX done interrupt

|                          | _UART1_RX_FIFO_ | RX FIFO depth (power of 2, min 1)

|                          | fast IRQ channel 5 | TX done interrupt (see <<_processor_interrupts>>)

|                          | _UART1_TX_FIFO_ | TX FIFO depth (power of 2, min 1)

Obviously, UART1 has different addresses for

Obviously, UART1 has different addresses for the control register (`CTRL`) and the data register (`DATA`) - see the register map below.

the control register (`CTRL`) and the data register (`DATA`) – see the register map below. However, the

The register's bits/flags use the same bit positions and naming as for the primary UART. The RX and TX interrupts of UART1 are

register bits/flags use the same bit positions and naming. Furthermore, the "RX done" and "TX done" interrupts are

mapped to different CPU fast interrupt (FIRQ) channels.

mapped to different CPU fast interrupt channels.

encoded data words.

data words.

.12+<| `0xffffffd0` .12+<| `NEORV32_UART1.CTRL` <|`11:0` _UART_CT_BAUDxx_ ^| r/w <| 12-bit BAUD value configuration value

.21+<| `0xffffffd0` .21+<| `NEORV32_UART1.CTRL` <|`11:0` _UART_CTRL_BAUDxx_ ^| r/w <| 12-bit BAUD value configuration value

                                                <|`12` _UART_CT_SIM_MODE_ ^| r/w <| enable **simulation mode**

                                                <|`12` _UART_CTRL_SIM_MODE_ ^| r/w <| enable **simulation mode**

                                                <|`20` _UART_CT_RTS_EN_   ^| r/w <| enable RTS hardware flow control

                                                <|`13` _UART_CTRL_RX_EMPTY_ ^| r/- <| RX FIFO is empty

                                                <|`21` _UART_CT_CTS_EN_   ^| r/w <| enable CTS hardware flow control

                                                <|`14` _UART_CTRL_RX_HALF_  ^| r/- <| RX FIFO is at least half-full

                                                <|`22` _UART_CT_PMODE0_   ^| r/w .2+<| parity bit enable and configuration (`00`/`01`= no parity; `10`=even parity; `11`=odd parity)

                                                <|`15` _UART_CTRL_RX_FULL_  ^| r/- <| RX FIFO is full

                                                <|`23` _UART_CT_PMODE1_   ^| r/w

                                                <|`16` _UART_CTRL_TX_EMPTY_ ^| r/- <| TX FIFO is empty

                                                <|`24` _UART_CT_PRSC0_    ^| r/w .3+<| 3-bit baudrate clock prescaler select

                                                <|`17` _UART_CTRL_TX_HALF_  ^| r/- <| TX FIFO is at least half-full

                                                <|`25` _UART_CT_PRSC1_    ^| r/w

                                                <|`18` _UART_CTRL_TX_FULL_  ^| r/- <| TX FIFO is full

                                                <|`26` _UART_CT_PRSC2_    ^| r/w

                                                <|`19` -                    ^| r/- <| _reserved_, read as zero

                                                <|`27` _UART_CT_CTS_      ^| r/- <| current state of UART's CTS input signal

                                                <|`20` _UART_CTRL_RTS_EN_   ^| r/w <| enable RTS hardware flow control

                                                <|`28` _UART_CT_EN_       ^| r/w <| UART enable

                                                <|`21` _UART_CTRL_CTS_EN_   ^| r/w <| enable CTS hardware flow control

                                                <|`31` _UART_CT_TX_BUSY_  ^| r/- <| trasmitter busy flag

                                                <|`22` _UART_CTRL_PMODE0_   ^| r/w .2+<| parity bit enable and configuration (`00`/`01`= no parity; `10`=even parity; `11`=odd parity)