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Rev 69 |
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the RX FIFO _becomes_ at least half-full (-> _UART_CTRL_RX_HALF_ sets).
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the RX FIFO _becomes_ at least half-full (-> _UART_CTRL_RX_HALF_ sets).
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* If _UART0_TX_FIFO_ is greater than 1: If _UART_CTRL_TX_IRQ_ is `0` the TX interrupt goes pending when at least one entry
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* If _UART0_TX_FIFO_ is greater than 1: If _UART_CTRL_TX_IRQ_ is `0` the TX interrupt goes pending when at least one entry
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in the TX FIFO _becomes_ free (-> _UART_CTRL_TX_FULL_ clears). If _UART_CTRL_TX_IRQ_ is `1` the TX interrupt goes pending
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in the TX FIFO _becomes_ free (-> _UART_CTRL_TX_FULL_ clears). If _UART_CTRL_TX_IRQ_ is `1` the TX interrupt goes pending
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when the RX FIFO _becomes_ less than half-full (-> _UART_CTRL_TX_HALF_ clears).
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when the RX FIFO _becomes_ less than half-full (-> _UART_CTRL_TX_HALF_ clears).
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A **pending RX interrupt** request is cleared by any of the following operations:
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Once the RX or TX interrupt has become pending, it has to be explicitly cleared again by setting the
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* read access to `NEORV32_UART0.DATA` (for example to read incoming data)
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according `mip` CSR bit.
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* write access to `NEORV32_UART0.CTRL`
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* disabling the UART module
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A **pending TX interrupt** request is cleared by any of the following operations:
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* write access to `NEORV32_UART0.DATA` (for example to send more data)
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* write access to `NEORV32_UART0.CTRL`
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* disabling the UART module
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[TIP]
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A dummy write to to the control register (i.e. `NEORV32_UART0.DATA = NEORV32_UART0.DATA`)
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can be executed to acknowledge any interrupt.
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**Simulation Mode**
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**Simulation Mode**
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The default UART0 operation will transmit any data written to the `DATA` register via the serial TX line at
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The default UART0 operation will transmit any data written to the `DATA` register via the serial TX line at
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