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| `0b111` | 4096 | 4 294 967 296
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Whenever the internal timer overflows the watchdog executes one of two possible actions: Either a hard
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Whenever the internal timer overflows the watchdog executes one of two possible actions: Either a hard
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processor reset is triggered or an interrupt is requested at CPU's fast interrupt channel #0. The
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processor reset is triggered or an interrupt is requested at CPU's fast interrupt channel #0. The
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WDT_CTRL_MODE bit defines the action to be taken on an overflow: When cleared, the Watchdog will trigger an
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WDT_CTRL_MODE bit definess the action to be taken on an overflow: When cleared, the Watchdog will assert an
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IRQ, when set the WDT will cause a system reset. The configured actions can also be triggered manually at
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IRQ, when set the WDT will cause a system reset. The configured action can also be triggered manually at
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any time by setting the _WDT_CTRL_FORCE_ bit. The watchdog is reset by setting the _WDT_CTRL_RESET_ bit.
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any time by setting the _WDT_CTRL_FORCE_ bit. The watchdog is reset by setting the _WDT_CTRL_RESET_ bit.
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A watchdog interrupt can only occur if the watchdog is enabled and interrupt mode is enabled.
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A pending interrupt is cleared by either disabling the watchdog or by resetting the watchdog.
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The cause of the last action of the watchdog can be determined via the _WDT_CTRL_RCAUSE_ flag. If this flag is
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The cause of the last action of the watchdog can be determined via the _WDT_CTRL_RCAUSE_ flag. If this flag is
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zero, the processor has been reset via the external reset signal. If this flag is set the last system reset was
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zero, the processor has been reset via the external reset signal. If this flag is set the last system reset was
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initiated by the watchdog.
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initiated by the watchdog.
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The Watchdog control register can be locked in order to protect the current configuration. The lock is
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The Watchdog control register can be locked in order to protect the current configuration. The lock is
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