| Line 131... |
Line 131... |
_SYSINFO_FEATURES_MEM_EXT_ENDIAN_ flag in the processor's SYSINFO module (see section
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_SYSINFO_FEATURES_MEM_EXT_ENDIAN_ flag in the processor's SYSINFO module (see section
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<<_system_configuration_information_memory_sysinfo>> for more information).
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<<_system_configuration_information_memory_sysinfo>> for more information).
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**AXI4-Lite Connectivity**
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**AXI4-Lite Connectivity**
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The AXI4-Lite wrapper (`rtl/templates/system/neorv32_SystemTop_axi4lite.vhd`) provides a Wishbone-to-
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The AXI4-Lite wrapper (`rtl/system_integration/neorv32_SystemTop_axi4lite.vhd`) provides a Wishbone-to-
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AXI4-Lite bridge, compatible with Xilinx Vivado (IP packager and block design editor). All entity signals of
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AXI4-Lite bridge, compatible with Xilinx Vivado (IP packager and block design editor). All entity signals of
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this wrapper are of type _std_logic_ or _std_logic_vector_, respectively.
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this wrapper are of type _std_logic_ or _std_logic_vector_, respectively.
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The AXI Interface has been verified using Xilinx Vivado IP Packager and Block Designer. The AXI
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The AXI Interface has been verified using Xilinx Vivado IP Packager and Block Designer. The AXI
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interface port signals are automatically detected when packaging the core.
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interface port signals are automatically detected when packaging the core.
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| Line 143... |
Line 143... |
.Example AXI SoC using Xilinx Vivado
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.Example AXI SoC using Xilinx Vivado
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image::neorv32_axi_soc.png[]
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image::neorv32_axi_soc.png[]
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[WARNING]
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[WARNING]
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Using the auto-termination timeout feature (_MEM_EXT_TIMEOUT_ greater than zero) is **not AXI4 compliant** as the AXI protocol does not support canceling of
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Using the auto-termination timeout feature (_MEM_EXT_TIMEOUT_ greater than zero) is **not AXI4 compliant** as the AXI protocol does not support canceling of
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bus transactions. Therefore, the NEORV32 top wrapper with AXI4-Lite interface (`rtl/templates/system/neorv32_SystemTop_axi4lite`) configures _MEM_EXT_TIMEOUT_ = 0 by default.
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bus transactions. Therefore, the NEORV32 top wrapper with AXI4-Lite interface (`rtl/system_integration/neorv32_SystemTop_axi4lite`) configures _MEM_EXT_TIMEOUT_ = 0 by default.
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bus transactions. Therefore, the NEORV32 top wrapper with AXI4-Lite interface (`rtl/system_integration/neorv32_SystemTop_axi4lite`) configures _MEM_EXT_TIMEOUT_ = 0 by default.
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bus transactions. Therefore, the NEORV32 top wrapper with AXI4-Lite interface (`rtl/system_integration/neorv32_SystemTop_axi4lite`) configures _MEM_EXT_TIMEOUT_ = 0 by default.
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