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https://opencores.org/ocsvn/neorv32/neorv32/trunk
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configuration registers.
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configuration registers.
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[TIP]
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[TIP]
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An example program for the XIP module is available in `sw/example/demo_xip`.
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An example program for the XIP module is available in `sw/example/demo_xip`.
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[WARNING]
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Debugging XIP code execution using the on-chip debugger is constrained. The debugger cannot insert breakpoints
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(`ebreak` instructions) into XIP code as the XIP access is read-only.
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[NOTE]
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[NOTE]
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Quad-SPI (QSPI) support, which is about 4x times faster, is planned for the future. 😉
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Quad-SPI (QSPI) support, which is about 4x times faster, is planned for the future. 😉
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**SPI Protocol**
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**SPI Protocol**
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Example: to map the XIP flash to the address space starting at `0x20000000` write a "2" (`0b0010`) to the _XIP_CTRL_XIP_PAGE_
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Example: to map the XIP flash to the address space starting at `0x20000000` write a "2" (`0b0010`) to the _XIP_CTRL_XIP_PAGE_
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control register bits. Any access within `0x20000000 .. 0x2fffffff` will be forwarded to the XIP flash.
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control register bits. Any access within `0x20000000 .. 0x2fffffff` will be forwarded to the XIP flash.
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Note that the SPI access address might wrap around.
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Note that the SPI access address might wrap around.
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.Using the FPGA Bitstream Flash also for XIP
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[TIP]
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You can also use the FPGA's bitstream SPI flash for storing XIP programs. To prevent overriding the bitstream,
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a certain offset needs to be added to the executable (which might require linker script modifications).
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To execute the program stored in the SPI flash simply jump to the according base address. For example
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if the executable starts at flash offset `0x8000` and the XIP flash is mapped to the base address `0x20000000`
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then add the offset to the base address and use that as jump/call destination (=`0x20008000`).
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**Using the XIP Mode**
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**Using the XIP Mode**
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The XIP module is globally enabled by setting the _XIP_CTRL_EN_ bit in the device's `CTRL` control register.
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The XIP module is globally enabled by setting the _XIP_CTRL_EN_ bit in the device's `CTRL` control register.
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Clearing this bit will reset the whole module and will also terminate any pending SPI transfer.
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Clearing this bit will reset the whole module and will also terminate any pending SPI transfer.
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