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Interrupt channel `xirq_i(0)` has highest priority and `xirq_i(_XIRQ_NUM_CH_-1)` has lowest priority.
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Interrupt channel `xirq_i(0)` has highest priority and `xirq_i(_XIRQ_NUM_CH_-1)` has lowest priority.
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This priority assignment is fixed and cannot be altered by software.
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This priority assignment is fixed and cannot be altered by software.
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The CPU can use the ID from `SCR` to service IRQ according to their priority. To acknowledge the according
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The CPU can use the ID from `SCR` to service IRQ according to their priority. To acknowledge the according
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interrupt the CPU can write `1 << SCR` to `IPR`.
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interrupt the CPU can write `1 << SCR` to `IPR`.
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In order to clear a pending FIRQ interrupt from the external interrupt controller again, the according `mip` CSR bit has
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In order to clear a pending FIRQ interrupt from the external interrupt controller again, the according <<_mip>> CSR bit has
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to be set. Additionally, the XIRQ interrupt has to be acknowledged by writing _any_
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to be cleared. Additionally, the XIRQ interrupt has to be acknowledged by writing _any_
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value to the interrupt source register `SRC`.
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value to the interrupt source register `SRC`.
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[NOTE]
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[NOTE]
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An interrupt handler should clear the interrupt pending bit that caused the interrupt first before
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An interrupt handler should clear the interrupt pending bit that caused the interrupt first before
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acknowledging the interrupt by writing the `SCR` register.
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acknowledging the interrupt by writing the `SCR` register.
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