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## HArdware RTL Sources
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## Hardware RTL Sources
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### [`core`](https://github.com/stnolting/neorv32/tree/main/rtl/core)
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### [`core`](https://github.com/stnolting/neorv32/tree/main/rtl/core)
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This folder contains the core VHDL files for the NEORV32 CPU and the NEORV32 Processor.
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This folder contains the core VHDL files for the NEORV32 CPU and the NEORV32 Processor.
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:warning: The sub-folder [`core/mem`](https://github.com/stnolting/neorv32/tree/main/rtl/core/mem)
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:warning: The sub-folder [`core/mem`](https://github.com/stnolting/neorv32/tree/main/rtl/core/mem)
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contains the _platform-agnostic_ VHDL architectures of the processor-internal memories.
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contains the _platform-agnostic_ VHDL architectures of the processor-internal memories.
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You can _replace_ inclusion of these files by platform-optimized memory architectures.
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You can _replace_ inclusion of these files by platform-optimized memory architectures.
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### [`processor_templates`](https://github.com/stnolting/neorv32/tree/main/rtl/processor_templates`)
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### [`processor_templates`](https://github.com/stnolting/neorv32/tree/main/rtl/processor_templates)
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Contains pre-configured "SoC" templates that instantiate the processor's top entity from `core`.
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Contains pre-configured "SoC" templates that instantiate the processor's top entity from `core`.
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These templates can be instantiated directly within a FPGA-specific board wrapper.
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These templates can be instantiated directly within a FPGA-specific board wrapper.
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### [`system_integration`](https://github.com/stnolting/neorv32/tree/main/rtl/system_integration`)
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### [`system_integration`](https://github.com/stnolting/neorv32/tree/main/rtl/system_integration)
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Top entities in this folder provide the same peripheral/IO signals and configuration generics as the default
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Top entities in this folder provide the same peripheral/IO signals and configuration generics as the default
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processor top entity from `core`, but feature a different interface type.
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processor top entity from `core`, but feature a different interface type.
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For example: an **AXI4-Lite**-compatible bus interface instead of the default Wishbone bus interface
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For example: an **AXI4-Lite**-compatible bus interface instead of the default Wishbone bus interface
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or a top entity with _resolved_ port signal types.
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or a top entity with _resolved_ port signal types.
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### [`test_setups`](https://github.com/stnolting/neorv32/tree/main/rtl/test_setups`)
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### [`test_setups`](https://github.com/stnolting/neorv32/tree/main/rtl/test_setups)
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Minimal test setups (FPGA- and board-independent) for the processor. See the
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Minimal test setups (FPGA- and board-independent) for the processor. See the
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[README](https://github.com/stnolting/neorv32/tree/main/rtl/test_setups)
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[README](https://github.com/stnolting/neorv32/tree/main/rtl/test_setups)
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in that folder for more information. Note that these test setups are used in the
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in that folder for more information. Note that these test setups are used in the
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[NEORV32 USer Guide](https://stnolting.github.io/neorv32/ug).
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[NEORV32 USer Guide](https://stnolting.github.io/neorv32/ug).
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