| Line 70... |
Line 70... |
cb_bus_re_i : in std_ulogic; -- read enable
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cb_bus_re_i : in std_ulogic; -- read enable
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cb_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
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cb_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
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cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
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cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
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cb_bus_err_o : out std_ulogic; -- bus transfer error
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cb_bus_err_o : out std_ulogic; -- bus transfer error
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-- peripheral bus --
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-- peripheral bus --
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p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B
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p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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p_bus_we_o : out std_ulogic; -- write enable
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p_bus_we_o : out std_ulogic; -- write enable
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| Line 186... |
Line 187... |
-- arbiter defaults --
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-- arbiter defaults --
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arbiter.state_nxt <= arbiter.state;
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arbiter.state_nxt <= arbiter.state;
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arbiter.bus_sel <= '0';
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arbiter.bus_sel <= '0';
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arbiter.we_trig <= '0';
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arbiter.we_trig <= '0';
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arbiter.re_trig <= '0';
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arbiter.re_trig <= '0';
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--
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p_bus_src_o <= '0';
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-- state machine --
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-- state machine --
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case arbiter.state is
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case arbiter.state is
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when IDLE => -- Controller a has full bus access
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when IDLE => -- Controller a has full bus access
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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p_bus_src_o <= '0'; -- access from port A
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if (ca_req_current = '1') then -- current request?
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if (ca_req_current = '1') then -- current request?
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arbiter.bus_sel <= '0';
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arbiter.bus_sel <= '0';
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arbiter.state_nxt <= BUSY;
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arbiter.state_nxt <= BUSY;
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elsif (ca_req_buffered = '1') then -- buffered request?
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elsif (ca_req_buffered = '1') then -- buffered request?
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arbiter.bus_sel <= '0';
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arbiter.bus_sel <= '0';
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| Line 208... |
Line 212... |
arbiter.state_nxt <= RETIRE_SWITCHED;
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arbiter.state_nxt <= RETIRE_SWITCHED;
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end if;
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end if;
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when BUSY => -- transaction in progress
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when BUSY => -- transaction in progress
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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p_bus_src_o <= '0'; -- access from port A
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arbiter.bus_sel <= '0';
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arbiter.bus_sel <= '0';
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if (ca_bus_cancel_i = '1') or -- controller cancels access
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if (ca_bus_cancel_i = '1') or -- controller cancels access
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(p_bus_err_i = '1') or -- peripheral cancels access
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(p_bus_err_i = '1') or -- peripheral cancels access
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(p_bus_ack_i = '1') then -- normal termination
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(p_bus_ack_i = '1') then -- normal termination
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arbiter.state_nxt <= IDLE;
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arbiter.state_nxt <= IDLE;
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end if;
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end if;
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when RETIRE => -- retire pending access
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when RETIRE => -- retire pending access
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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p_bus_src_o <= '0'; -- access from port A
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arbiter.bus_sel <= '0';
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arbiter.bus_sel <= '0';
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if (PORT_CA_READ_ONLY = false) then
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if (PORT_CA_READ_ONLY = false) then
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arbiter.we_trig <= ca_wr_req_buf;
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arbiter.we_trig <= ca_wr_req_buf;
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end if;
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end if;
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arbiter.re_trig <= ca_rd_req_buf;
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arbiter.re_trig <= ca_rd_req_buf;
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arbiter.state_nxt <= BUSY;
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arbiter.state_nxt <= BUSY;
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when BUSY_SWITCHED => -- switched transaction in progress
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when BUSY_SWITCHED => -- switched transaction in progress
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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p_bus_src_o <= '1'; -- access from port B
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arbiter.bus_sel <= '1';
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arbiter.bus_sel <= '1';
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if (cb_bus_cancel_i = '1') or -- controller cancels access
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if (cb_bus_cancel_i = '1') or -- controller cancels access
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(p_bus_err_i = '1') or -- peripheral cancels access
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(p_bus_err_i = '1') or -- peripheral cancels access
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(p_bus_ack_i = '1') then -- normal termination
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(p_bus_ack_i = '1') then -- normal termination
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arbiter.state_nxt <= IDLE;
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arbiter.state_nxt <= IDLE;
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end if;
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end if;
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when RETIRE_SWITCHED => -- retire pending switched access
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when RETIRE_SWITCHED => -- retire pending switched access
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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p_bus_src_o <= '1'; -- access from port B
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arbiter.bus_sel <= '1';
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arbiter.bus_sel <= '1';
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if (PORT_CB_READ_ONLY = false) then
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if (PORT_CB_READ_ONLY = false) then
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arbiter.we_trig <= cb_wr_req_buf;
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arbiter.we_trig <= cb_wr_req_buf;
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end if;
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end if;
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arbiter.re_trig <= cb_rd_req_buf;
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arbiter.re_trig <= cb_rd_req_buf;
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