| Line 57... |
Line 57... |
ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
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ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
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ca_bus_we_i : in std_ulogic; -- write enable
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ca_bus_we_i : in std_ulogic; -- write enable
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ca_bus_re_i : in std_ulogic; -- read enable
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ca_bus_re_i : in std_ulogic; -- read enable
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ca_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
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ca_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
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ca_bus_lock_i : in std_ulogic; -- locked/exclusive access
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ca_bus_excl_i : in std_ulogic; -- exclusive access
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ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
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ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
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ca_bus_err_o : out std_ulogic; -- bus transfer error
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ca_bus_err_o : out std_ulogic; -- bus transfer error
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-- controller interface b --
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-- controller interface b --
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cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
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cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
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cb_bus_we_i : in std_ulogic; -- write enable
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cb_bus_we_i : in std_ulogic; -- write enable
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cb_bus_re_i : in std_ulogic; -- read enable
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cb_bus_re_i : in std_ulogic; -- read enable
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cb_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
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cb_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
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cb_bus_lock_i : in std_ulogic; -- locked/exclusive access
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cb_bus_excl_i : in std_ulogic; -- exclusive access
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cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
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cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
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cb_bus_err_o : out std_ulogic; -- bus transfer error
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cb_bus_err_o : out std_ulogic; -- bus transfer error
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-- peripheral bus --
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-- peripheral bus --
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p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B
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p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B
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p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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| Line 80... |
Line 80... |
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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p_bus_we_o : out std_ulogic; -- write enable
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p_bus_we_o : out std_ulogic; -- write enable
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p_bus_re_o : out std_ulogic; -- read enable
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p_bus_re_o : out std_ulogic; -- read enable
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p_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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p_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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p_bus_lock_o : out std_ulogic; -- locked/exclusive access
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p_bus_excl_o : out std_ulogic; -- exclusive access
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p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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p_bus_err_i : in std_ulogic -- bus transfer error
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p_bus_err_i : in std_ulogic -- bus transfer error
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);
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);
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end neorv32_busswitch;
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end neorv32_busswitch;
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| Line 264... |
Line 264... |
p_bus_we <= ca_bus_we_i when (arbiter.bus_sel = '0') else cb_bus_we_i;
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p_bus_we <= ca_bus_we_i when (arbiter.bus_sel = '0') else cb_bus_we_i;
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p_bus_re <= ca_bus_re_i when (arbiter.bus_sel = '0') else cb_bus_re_i;
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p_bus_re <= ca_bus_re_i when (arbiter.bus_sel = '0') else cb_bus_re_i;
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p_bus_cancel_o <= ca_bus_cancel_i when (arbiter.bus_sel = '0') else cb_bus_cancel_i;
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p_bus_cancel_o <= ca_bus_cancel_i when (arbiter.bus_sel = '0') else cb_bus_cancel_i;
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p_bus_we_o <= (p_bus_we or arbiter.we_trig);
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p_bus_we_o <= (p_bus_we or arbiter.we_trig);
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p_bus_re_o <= (p_bus_re or arbiter.re_trig);
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p_bus_re_o <= (p_bus_re or arbiter.re_trig);
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p_bus_lock_o <= ca_bus_lock_i or cb_bus_lock_i;
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p_bus_excl_o <= ca_bus_excl_i or cb_bus_excl_i;
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ca_bus_rdata_o <= p_bus_rdata_i;
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ca_bus_rdata_o <= p_bus_rdata_i;
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cb_bus_rdata_o <= p_bus_rdata_i;
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cb_bus_rdata_o <= p_bus_rdata_i;
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ca_bus_ack <= p_bus_ack_i and (not arbiter.bus_sel);
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ca_bus_ack <= p_bus_ack_i and (not arbiter.bus_sel);
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